Question

Complete the timing diagram of Fig. P4.14b by drawing the waveforms of signals

4.14 The circuit of Fig. P4.14a contains a D latch, a positive-edge-triggered D flip-flop, and a negative-edge-triggered D flip-flop. Complete the timing diagram of Fig. P4.14b by drawing the waveforms of signals,, and y FI D O Clack Clock Figure P4.14: a. Logic diagram. B. Timing diagram.

Answer 1

The given circuit is as shown in Figure 1 Y3 Clock Figure 1 Figure 1 contains a D latch, a positive edge triggered D flip-flop and a negative edge triggered D flip-flop. The given timing diagram with clock and input 1s as shown in Figure -2 Clock Figure 2 D Flip-flop means data flip flop. This flip-flop stores the value on the data line. That is when D 0, the next state output Q-0 and when D-1, the next state output Q- From Figure 1, y, is the output of D latch with clock as enable input. When C-0, the next state holds the value of the previous sate. When C1, the next state values are as shown in Table 1· y, is the output of positive edge triggered D flip-flop, that is the output changes with respect to input on the rising edge of the clock. y, is the output of negative edge triggered D flip-flop, that is the output changes with respect to input on the falling edge of the clock.

The excitation table for D flip-flop is as shown in Table1 DQİQ 0 0 0 0 store 0 10 1 store 1 Table 1 From Table 1, the output waveform for y,, y, and y, with respect to clock and input is as shown in Figure 3 Clock yi Figure 3 Therefore, the complete timing diagram of Figure 2 is as shown in Figure 3