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A. Ch. 3.4 - Tomasulos Algorithm We are given the following MIPS code with the following latencies: Latency L.D MULT.D L.D F

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Answer #1

L.D F2, 0(R2) - 2 cycle latency

MULT.D F8, F6, F2   - 3 cycle latency

L.D F4,4(R4) - 2 cycle latency

ADD.D F12, F0, F4   - 1 cycle latency

ADD.D F10, F8, F2   - 1 cycle latency

At cycle 1

First load instruction is issued

Instruction status

Instruction Issue Execute Write back
L.D F2, 0(R2) 1

Reservation status

Name Busy Op Vj Vk Qj Qk A
load1 yes load 0+R2
load2
add1
add2
mult1
mult2

Register status

F0 F2 F4 F6 F8 F10 F12 ---- F30
load1

At cycle 2

Multiplication instruction is issued

Instruction status

Instruction Issue Execute Write back
L.D F2, 0(R2) 1
MULT.D F8, F6, F2 2

Reservation status

Name Busy Op Vj Vk Qj Qk A
load1 yes load 0+R2
load2
add1
add2
mult1 yes mult F6 load1
mult2

Register status

F0 F2 F4 F6 F8 F10 F12 ---- F30
load1 mult1

At cycle 3

Second load instruction is issued

First load instruction completes its execution

Instruction status

Instruction Issue Execute Write back
L.D F2, 0(R2) 1 3
MULT.D F8, F6, F2 2
L.D F4,4(R4) 3

Reservation status

Na​​​​​​​me Busy Op Vj Vk Qj Qk A
load1
load2 yes load 4+R4
add1
add2
mult1 yes mult F6 load1
mult2

Register status

F0 F2 F4 F6 F8 F10 F12 ---- F30
load1 load2 mult1

At cycle 4

First add instruction is issued

First load instruction writes result and broadcast it

Multiply instruction will start its execution

Instruction status

Instruction Issue Execute Write back
L.D F2, 0(R2) 1 3 4
MULT.D F8, F6, F2 2
L.D F4,4(R4) 3
ADD.D F12, F0, F4 4

Reservation status

Na​​​​​​​me Busy Op Vj Vk Qj Qk A
load1
load2 yes load 4+R4
add1 yes add F0 load2
add2
mult1 yes mult F6 F2
mult2

Register status

F0 F2 F4 F6 F8 F10 F12 ---- F30
load2 mult1 add1
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