Given a static multiple issue unit for the MIPS processor where the system can do a...

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ints) where the system can do a Given a static multiple issue unit for the MIPs processor instruction with a sot is instruction with one issue slot and a loadstore a second issue slot. The instructions can not be dependent on one another and, code unable to be filled with an instruction it is filed with a NOP Given the following see show the contents of the separate slots below. How much of a speedup wil you over a standard single issue unit? sro, 20 ($r6) add $0, sro, $r1 add 2, 3, sro, 24(sr6) ALU/Branch Clock Cycle

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Answer: Clock cycle Load/store ALU/Branch NOP add SrO, Sr0, Srl NOP add Sr2, Sr3, Sr4 NOP lw Sro, 20(Sr6) NOP sw Sr1, 48(Sr6)

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Given a static multiple issue unit for the MIPS processor where the system can do a...

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