Question

Computer Architecture

14. Fill in the blanks below with the most appropriate term or concept discussed in this chapter:

A. ---------------The time required for the first result in a series of computations to emerge from a pipeline.

B. ---------------This is used to separate one stage of a pipeline from the next.

C. ---------------Over time, this tells the mean number of operations completed by a pipeline per clock cycle.

D. ---------------The clock cycles that are wasted by an instruction-pipelined processor due to executing a control transfer instruction.

E. ---------------A technique used in pipelined CPUs when the compiler supplies a hint as to whether a given conditional branch is likely to succeed.

F. ---------------The instruction(s) immediately following a conditional control transfer instruction in some pipelined processors, which are executed whether the control transfer occurs.

G. --------------A technique used in pipelined CPUs when the instruction immediately following another instruction

that reads a memory operand cannot use the updated value of the operand.

H. --------------The most common data hazard in pipelined processors—also known as a true data dependence.

I. ---------------Also known as an output dependence, this hazard can occur in a processor that utilizes out-of-order

execution.

J. --------------A centralized resource scheduling mechanism for internally concurrent processors; it was first used in

the CDC 6600 supercomputer.

K. --------------These are used by a Tomasulo scheduler to hold operands for functional units.

L. ---------------A technique used in some RISC processors to speed up parameter passing for high-level language procedure calls.

M. --------------This type of processor architecture maximizes temporal parallelism by using a very deep pipeline with very fast stages.

N. --------------This approach to high-performance processing uses multiple pipelines with resolution of interinstruction data dependencies done by the control unit.

O. --------------The “architecture technology” used in Intel’s IA-64 (Itanium) chips.

P. ---------------The Itanium architecture uses this approach instead of branch prediction to minimize the disruption caused by conditional control transfers.

Q. --------------A machine using this technique can issue instructions from more than one thread of execution during the same clock cycle.

Answer 1

A. flow tgrough time

B. Pipeline register

C. Pipeline throughput

D. Branch penalty

E. Static branch prediction

F. Delay slot instruction

G. Delayed load

H. RAW hazard (Read After Write)

I. WAW Hazard (Write After Write)

J. Scoreboard.

K. Reservation Station

It can buffer the instruction as well as the operands of the instruction.

L. Overlapping register window

register windows are a feature in instruction set architectures to improve the performance of a procedure.

M. Superpipelined

A technique that improves the performance of a processor. It splits instructions into many separate "pipelines" that can be executed more instructions in parallel.

N. Superscalar

A superscalar processor is a CPU which implements a form of parallelism called instruction-level parallelism within a single processor.

O) EPIC (Explicitly Parallel Instruction Computing)

is a 64-bit microprocessor instruction set, that provides up to 128 general and floating point unit registers and uses speculative loading, predication.

P) Predication

Predication is a technique that tries to reduce pipeline stalls due to control hazards. It allows branches to removed from the code.

Q) Parrallelism

It means multiple perations performing at the same clock cycle.