Question

For pipelined execution, there are multiple instructions on the pipeline for concurrent execution. How the control unit is designed inside the processor? Choose one most appropriate answer below. Use multiple control units each controlling the execution of one instruction. Control signals are generated at ID stage, and propagates via pipeline buffers to next stage(s) along with instruction execution. Control signals are pre-stored in the pipeline buffers. When an instruction reaches to a certain stage, it will use the signals stored there. None of above description as good as mine. Here’s my description: ____________________

Answer 1

The appropriate answer out of your options is-

Control signals are generated at Instruction Decode stage and propagates via pipeline buffers to next stage along with Instruction execution.

Explanation:

As the decoded instruction will tell the next command to be carried out, control signals are then generated according to the condition. There will be multiple instructions and the pipelined execution will help in reducing the clock cycles which provides quicker results. Control signals are generated after the decode phase. First phase is Fetch and then the sequence is followed Decode, Execute, Memory, Write Back.

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