Question

D3 Vou 2) (30p) Yandaki devrede kullanılan bütün R diyotlar silisyum yapıdadır. D. diyoduna ait zener 0M + gerilimi 8 V, D. diyoduna ait zener gerilimi 5.6 V olarak verilmiştir. Uygulanan giriş gerilimi Vin=20 sin(wt) V olarak belirlenmiştir. Devrenin çıkış Vin geriliminin uygulanan V, gerilimine göre değişimini devreyi analiz ederek çiziniz. (Analiz yapılmadan gerçekleştirilen doğru çizimler değerlendirmeye alinmayacaktır. Diyot elemanının basitleştirilmiş modeli kullanılacaktır.) it of o

All the diodes used in the circuit are silicon. Zener voltage of D2 diode is given as 8 V and zener voltage of D4 diode is given as 5.6 V. Applied input voltage is determined as Vin = 20 sin (ωt) V. Draw the change of the output voltage of the circuit according to the applied voltage by analyzing the circuit. (Correct drawings made without analysis will not be evaluated. Simplified model of diode element will be used.)

Answer 1

During positive half cycle of imports Diode D FB and BB D3 Dy and FB D₂ ЕВ when Viy > (vo,+ vzn) Amo (, and ) Start's conduetion Vo = Vp +22= 0748 8.7V when Vo - Venc-(Vogtlay) Arme (0, and Dy) starts conduction -(Voz + Vzu) = -0.4-5-67= -6.3 V Dioder cre not in conduction In between S.TV and -6.3V . Vout Vin Viy 20V $ -20 V Vo DEFB = zeroy breakdown 8.75 D3-FR (Dy Zener Breakobcom -6-3 All an ciorenit core open

when V_in > 0.7 V diode D1 in forward bias but the diode D2 in reverse bias......when V_in reaches 8.7 V zener breakdown occurs.....D1 and D2 starts conduction .... circuit becomes (when V_in > 8.7 V)

R M K 7 Voi Nin 0-761 Mo-8.7V 1 Z

when V_in < -0.7 V diode D3 in forward bias but the diode D4 in reverse bias......when V_in reaches -6.3 V zener breakdown occurs.....D3 and D4 starts conduction .... circuit becomes (when V_in < -6.3 V)

R my K Iozy ㅏ Vo 63 Vim 56% V t fe

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