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Example on Cache Placement & Misses -

Can someone explain to me how this is done.

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Consider a small direct-mapped cache with 32 block

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Answer #1

Hit: If the processor finds that the memory location is in the cache, a cache hit has occurred.

Miss: If the processor does not find the memory location in the cache, a cache miss has occurred.

How to start:

First figure out the bits of the offset (the right-most bits of the address),
then figure out the bits of the index (the next-to right-most address bits),
and then the tag is everything left over (on the left side).

One way to think of a direct mapped cache is as a table with rows and columns.
The index tells you what row to look at, then you compare the tag for that row,
and if it matches, the offset tells you which column to use.

By following in this way, you can find the Hit/Miss for each memory address reference:

row column
Address
Hexadecimal
Binary Representation Tag
(23)
Index
(5)
Offset
(4)
Hit/Miss Reason
0x3E8 …0000 0011 1110 1000 1 1E 8 Miss First time Accessing this address.
So It will not be in cache and hence miss.
During this access, 32 blocks of data(row 1E) gets stored in cache.
0x3EC ...0000 0011 1110 1100 1 1E C Hit As the data of row 1E is available in cache in Step1,
it can be accessed from cache and hence it is Hit
0x3F0 ...0000 0011 1111 0000 0 F 0 Miss Accessing the row F for the first time.
So it will not be there in cache. Hence Miss.
0x9F4 ...0000 1001 1111 0100 1 7 4 Miss Accessing the row 7 for the first time.
So it will not be there in cache. Hence Miss.
0x9F8 ...0000 1001 1111 1000 1 7 8 Hit Data of row 7 will be available in cache after step 4.
So it can be accessed from cache. Hence it is Hit
0x9FC ...0000 1001 1111 1100 1 7 C Hit Data of row 7 will be available in cache after step 4.
So it can be accessed from cache. Hence it is Hit
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