Question

Implement a 1011 Moore sequence detector in Verilog. In addition to detecting the sequence, the circuit keeps track of modulo-256 count of the 1011 sequences ever detected. When the correct sequence is detected, the w output becomes 1 and at the same time an 8-bit counter is incremented.

A. Show the state diagram for this circuit.

B. Describe the circuit in a synthesizable Verilog code. Use this for simulation by ModelSim.

C. Write a testbench for the circuit in Verilog that tests the correctness of your circuit.

Answer 1

Implement a 1011 Moore sequence detector in Verilog.

The Moore FSM keeps detecting a binary sequence from a digital input and the output of FSM which goes high only when a "1011" sequence is detected.

(A) The state diagram of the Moore FSM for a sequence detector is shown in figure below -

0 One OneZero RESET 0 Zero /0 0 0 0 OneZeroOne /0 OneZeroOneOne

We know that, the Moore FSM output depends on the current state of the FSM.

(B) Describe the circuit in a synthesizable Verilog code. Use this for simulation by ModelSim.

current state detector_out sequence_in next state State Next State Combinational Logic レ | Output Logic Memory reset clock

(C) Write a testbench for the circuit in Verilog that tests the correctness of our circuit.

$\Rightarrow$ Verilog Testbench for sequence detector using Moore FSM which is given as -

module tb_Sequence_Detector_Moore_FSM_Verilog ;

// Inputs

reg sequence_in ;

reg clock ;

reg reset ;

// Outputs

wire detector_out ;

// Instantiate the Sequence Detector using Moore FSM

Sequence_Detector_Moore_FSM_Verilog uut

{

.sequence_in (sequence_in) ,

.clock (clock) ,

.reset (reset) ,

.detector_out (detector_out)

} ;

initial begin

clock = 0 ;

forever #5 clock $= \sim$ clock ;

end

initial begin

// Initialize Inputs

sequence_in = 0 ;

reset = 1 ;

// wait 100 ns for global reset to finish

#30 ;

reset = 0 ;

#40 ;

sequence_in = 1 ;

#10 ;

sequence_in = 0 ;

#10 ;

sequence_in = 1 ;

#20 ;

sequence_in = 0 ;

#20 ;

sequence_in = 1 ;

#20 ;

sequence_in = 0 ;

// Add stimulus here

end

endmodule