Question

Incorrect 0/1 pts Question 10 Suppose that we have an L1 cache of this configuration: • B = 32 bytes • S= 64 • E = 1 • C = 20

0 0
Add a comment Improve this question Transcribed image text
Answer #1

Solution:

Given Block Size = 32 Bytes = 25B I No. of sets = 64 Cache Capacity = 2048 Bytes=2 B and the size of 1 Struct variable will b

Add a comment
Know the answer?
Add Answer to:
Incorrect 0/1 pts Question 10 Suppose that we have an L1 cache of this configuration: •...
Your Answer:

Post as a guest

Your Name:

What's your source?

Earn Coins

Coins can be redeemed for fabulous gifts.

Not the answer you're looking for? Ask your own homework help question. Our experts will answer your question WITHIN MINUTES for Free.
Similar Homework Help Questions
  • D Question 10 1 pts Suppose that we have an L1 cache of this configuration: •...

    D Question 10 1 pts Suppose that we have an L1 cache of this configuration: • B=32 bytes • S= 64 • E = 1 • C = 2048 bytes What is the cache miss rate (as a percentage) when we execute the following C code? Assume that the grid data structure is aligned on a cache block boundary in memory and that the cache is cold. struct { double x; double y; } grid[16][16]; for(i = 0; i <...

  • Suppose that we have an L1 cache of this configuration: Block size 32 bytes Number of...

    Suppose that we have an L1 cache of this configuration: Block size 32 bytes Number of sets 64 Associativity = 1 Capacity-2048 bytes What is the cache miss rate (as a percentage) when we execute the following C code? Assume that the grid data structure is aligned on a cache block boundary in memory and that the cache contains no valid lines initially. struct double x; double y; grid[16] [16]; forCi = 0; i < 16; i++) for(j 0; j...

  • 2. Cache hierarchy You are building a computer system with in-order execution that runs at 1...

    2. Cache hierarchy You are building a computer system with in-order execution that runs at 1 GHz and has a CPI of 1, with no memory accesses. The memory system is a split L1 cache. Both the I-cache and the D-cache are direct mapped and hold 32 KB each, with a block size of 64 bytes. The memory system is split L1 cache. Both the I-cache and the D-cache are direct mapped and hold 32 KB each, with a block...

  • Cache performance The starting code would have: struct position { int x; int y; } int...

    Cache performance The starting code would have: struct position { int x; int y; } int N; struct position grid[N][N]; int totalX=0; int totalY=0; int i, j; //For X loop for( i = 0; i < N; i ++){ for( j = 0; j < N; j++){ totalX += grid[i][j].x; } } //For Y loop for( j = 0; j < N; j++){ for( i = 0; i < N; i++){ totalY += grid[i][j].y; } } Part I: This part...

  • Problem 6. Suppose we have a computer with 32 megabytes of main memory, 256 bytes of...

    Problem 6. Suppose we have a computer with 32 megabytes of main memory, 256 bytes of cache, and a block size of 16 bytes. For each configuration below, determine the memory address format, indicating the number of bits needed for each appropriate field (i.e. tag, block, set, offset). Show any relevant calculations. Direct cache mapping and memory is byte-addressable a) Direct cache mapping and memory is word-addressable with a word size of 16 bits b) c) 2-way set associative cache...

  • Suppose we have a 32-bit MIPS processor, which includes a 2-way set associative data cache with...

    Suppose we have a 32-bit MIPS processor, which includes a 2-way set associative data cache with capacity 16384 bytes, 16 bytes block, and a least recently used (LRU) replacement policy. Assume that the cache is empty (all valid bits are 0) before the following code is executed. lw $t1, 0x1040($0) lw $t2, 0x2044($0) lw $t3, 0x3048($0) lw $t4, 0x1044($0) lw $t5, 0x504c($0) lw $t6, 0x3040($0) For each of the six assembly instructions above, state i) the set field value for...

  • Consider an L1 cache that has 8 sets, is direct-mapped (1-way), and supports a block size...

    Consider an L1 cache that has 8 sets, is direct-mapped (1-way), and supports a block size of 64 bytes. For the following memory access pattern (shown as byte addresses), show which accesses are hits and misses. For each hit, indicate the set that yields the hit. (30 points) 0, 48, 84, 32, 96, 360, 560, 48, 84, 600, 84, 48.

  • Consider a 64-bit computer with a simplified memory hierarchy. This hierarchy contains a single cache and...

    Consider a 64-bit computer with a simplified memory hierarchy. This hierarchy contains a single cache and an unbounded backing memory. The cache has the following characteristics: • Direct-Mapped, Write-through, Write allocate. • Cache blocks are 4 words each. • The cache has 256 sets. (a) Calculate the cache’s size in bytes. (b) Consider the following code fragment in the C programming language to be run on the described computer. Assume that: program instructions are not stored in cache, arrays are...

  • Assume you have: 32-bit addresses, 4KB Page size, 4MB Physical Memory Space, 4KB Cache with 4-way...

    Assume you have: 32-bit addresses, 4KB Page size, 4MB Physical Memory Space, 4KB Cache with 4-way set associative and LRU replacement, 32 Byte Cache block size, 4-entry fully associative TLB. A program to be run on this machine begins as follows:   double A[1024]; int i, j; double sum = 0; for( i = 0; i < 1024; i++ )       // first loop      A[i] = i; for( j = 0; j < 1024; j += 16 )   // second loop     ...

  • Question 29 7 pts Suppose we have a byte-addressable computer with a cache that holds 8...

    Question 29 7 pts Suppose we have a byte-addressable computer with a cache that holds 8 blocks of 4 bytes each. Assuming that each memory address has 8 bits, to which cache block would the hexadecimal address Ox1F map if the computer uses direct mapping?

ADVERTISEMENT
Free Homework Help App
Download From Google Play
Scan Your Homework
to Get Instant Free Answers
Need Online Homework Help?
Ask a Question
Get Answers For Free
Most questions answered within 3 hours.
ADVERTISEMENT
ADVERTISEMENT
ADVERTISEMENT