Question

Assume you have: 32-bit addresses, 4KB Page size, 4MB Physical Memory Space, 4KB Cache with 4-way set associative and LRU replacement, 32 Byte Cache block size, 4-entry fully associative TLB. A program to be run on this machine begins as follows:
  double A[1024];
int i, j;
double sum = 0;
for( i = 0; i < 1024; i++ )       // first loop
     A[i] = i;
for( j = 0; j < 1024; j += 16 )   // second loop
     sum += A[j];

The size of double is 8 bytes. Array A is located in memory starting at 0x1000 and stored in row major order. The cache and TLB are initially empty and NO pre-fetching is done. The only data memory references made by the program are those to array A.

1. How many bits are needed to specify the page offset? How many bits are needed to specify the physical page (frame) number? How many bits are needed to specify the virtual page number?
2. What is the hit rate for the cache in the first loop?
3. What is the hit rate for the cache in the second loop?
4. What is the TLB hit rate in the first loop?

Answer 1

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