4. If the memory bus has 24 bits, and there are 8 words in a block...
4. If the memory bus has 24 bits, and there are 8 words in a block in RAM, To design a 4 set-associative cache with 8K sets in cache, answer the following questions:
(a). RAM size
(b). How many blocks in RAM?
(c). How many bits are w?
(d). How many bits are d?
(e). How many bits are s?
(f). cache size in words?
(g). How many lines in cache?
(h). If we increase the cache size to 32K sets, state how d, s and size will change to accommodate the new larger cache (all other specifications are the same)
5. In a k-way set associative cache, discuss what happens when k=1 and k= total number of lines in cache, and how they performance of cache is affected?
Homework Answers
Hi
If the memory bus = Address bus = 24 bits
Total size of RAM = 2 power 24 = 16M
We are giving detail explanation below .
Add Answer to:
4. If the memory bus has 24 bits, and there are 8 words in a
block...
Suppose that a main memory has 8192 blocks each block having 32 words. Show the memory...
Suppose that a main memory has 8192 blocks each block having 32 words. Show the memory address format (see figures 4.10 and 4.12 of your textbook for examples) for each of the cache organizations below. a. a direct map cache with 64 lines of 32 words each b. a set associative cache with 16 sets each with four lines of 32 words each c. a fully associate cache with 128 lines of 32 words each PLEASE EXPLAIN IN DETAIL
7. In a cache system we have the following attributes: 4 GB of DRAM 256 MB...
7. In a cache system we have the following attributes: 4 GB of DRAM 256 MB of physical memory space 2 MB of cache IKB per cache line Determine number of lines in cache. a) Determine the number of address bits out of the processor. b) c) Determine the number of bits needed for the block offset section of the address. If our cache is 8-way set associative, how many sets are there in the cache? d) How many bits...
question 2 and 3 2. Determine how many sets of cache blocks will be there for...
question 2 and 3
2. Determine how many sets of cache blocks will be there for the following Cache memory size (in bytes) Direct Mapped Blocks Size (in bits) 32 64 218 2-way Set Associative Block Size (in bits) 32 64 A 2A6 [0.5 * 16 = 8] 4-way Set Associative Block Size (in bits) 32 64 SK 64K 256K 3. The physical memory address generated by a CPU is converted into cache memory addressing scheme using the following mapping...
A computer with a 24‐bit address bus has a main memory of size 16 MB and...
A computer with a 24‐bit address bus has a main memory of size 16 MB and a cache size of 64 KB. The word length is two bytes. a. What is the address format for a direct mapped cache with a line size of 32 words? b. What is the address format for a fully associative cache with a line size of 32 words? c. What is the address format for a 4‐way set associative cache with a line size...
A 64-bit word computer employs a 128KB cache. The address bus in this system is 32-bits....
A 64-bit word computer employs a 128KB cache. The address bus in this system is 32-bits. Determine the number of bits in each field of the memory address register (MAR) as seen by cache in the following organizations (show your calculations): a. Fully associative mapping with line size of 1 word. b. Fully associative mapping with line size of 4 words c. Direct mapping with the line size of 1 word. d. Direct mapping with the line size of 8...
Computer Architecture - Cache Problems 4, Suppose memory addresses are n bits long and the cache...
Computer Architecture - Cache Problems
4, Suppose memory addresses are n bits long and the cache can hold M bytes of data. If the cache block-size is 2 bytes and the cache is k-way set associative, what is the total size of the cache with a write-through policy? How would your answer change, if at all when the cache had a write-back policy?
Suppose a computer using set associative cache has 216 words of main memory and a cache...
Suppose a computer using set associative cache has 216 words of main memory and a cache of 32 blocks, and each cache block contains 8 words. 3. If this cache is 2-way set associative, what is the format of a memory address as seen by the cache, that is, what are the sizes of the tag, set, and word fields? If this cache is 4-way set associative, what is the format of a memory address as seen by the cache?...
Cache question computer architecture A cache holds 128 words where each word is 4 bytes. Assuming...
Cache question computer architecture A cache holds 128 words where each word is 4 bytes. Assuming a 32-bit address, for each of the following organizations, complete the table. a.A direct-mapped cache with block size = 16words b.2-way set-associative cache with block size = 8words c.4-way set-associative cache with block size = 4words d.A fully associative cache with block size = 2words. Cache a Cache b Cache c Cache d total # bits for word & byte displacement # bits in...
32 bytes of memory. 16 bytes of 2-way set-associative cache, where blocks can go anywhere within...
32 bytes of memory. 16 bytes of 2-way set-associative cache, where blocks can go anywhere within the set. Block is 2 bytes, set in cache is two blocks. Populate memory starting with upper-case letters, then 0-5. Hint- with full associativity in the set: each block has its own set of Tag bits in the cache. Memory is not organized by sets, though blocks get assigned to sets, and load in the cache per set. 1) Break down the addressing: Tag...
A primary memory system consists of 128 address bits. Each block within the cache is 256...
A primary memory system consists of 128 address bits. Each block within the cache is 256 bytes. The total cache size is 131,072 bytes. What are the sizes of the tag and index in the cache? First, find the number of blocks. 128,000 bytes # Blocks = 256 bytes per block bort = 512 blocks Where does the 128,000 come from?? Now find the number of bits required to distinguish all the blocks. This is the index aka set size....
7. In a cache system we have the following attributes: 4 GB of DRAM 256 MB of physical memory space 2 MB of cache IKB per cache line Determine number of lines in cache. a) Determine the number of address bits out of the processor. b) c) Determine the number of bits needed for the block offset section of the address. If our cache is 8-way set associative, how many sets are there in the cache? d) How many bits...
question 2 and 3
2. Determine how many sets of cache blocks will be there for the following Cache memory size (in bytes) Direct Mapped Blocks Size (in bits) 32 64 218 2-way Set Associative Block Size (in bits) 32 64 A 2A6 [0.5 * 16 = 8] 4-way Set Associative Block Size (in bits) 32 64 SK 64K 256K 3. The physical memory address generated by a CPU is converted into cache memory addressing scheme using the following mapping...
Computer Architecture - Cache Problems
4, Suppose memory addresses are n bits long and the cache can hold M bytes of data. If the cache block-size is 2 bytes and the cache is k-way set associative, what is the total size of the cache with a write-through policy? How would your answer change, if at all when the cache had a write-back policy?
Suppose a computer using set associative cache has 216 words of main memory and a cache of 32 blocks, and each cache block contains 8 words. 3. If this cache is 2-way set associative, what is the format of a memory address as seen by the cache, that is, what are the sizes of the tag, set, and word fields? If this cache is 4-way set associative, what is the format of a memory address as seen by the cache?...
A primary memory system consists of 128 address bits. Each block within the cache is 256 bytes. The total cache size is 131,072 bytes. What are the sizes of the tag and index in the cache? First, find the number of blocks. 128,000 bytes # Blocks = 256 bytes per block bort = 512 blocks Where does the 128,000 come from?? Now find the number of bits required to distinguish all the blocks. This is the index aka set size....
Most questions answered within 3 hours.
-
1. Which of the following is NOT an argument that McMahan uses
to show that jus...
asked 16 minutes ago -
A crate slides up a frictionless slope. At the end of 3 seconds
its velocity is...
asked 33 minutes ago -
Use the following information to answer the next seven
questions.
Suppose there are three potential states...
asked 29 minutes ago -
If we only have interstitial and substitutional diffusion, then
what do we consider the process of...
asked 45 minutes ago -
You look at yourself in a shiny 9.6-cm-diameter Christmas tree
ball.
If your face is 21.0...
asked 47 minutes ago -
If we were to measure the relaxation time of a muscle after
undergoing tetanus compared to...
asked 47 minutes ago -
4CO(g) + 8H2(g) -----> 3CH4(g) +
CO2(g) + 2H2O(l)
Use the following data as needed to...
asked 50 minutes ago -
without using map
1. Write a C++ program to find out the top 10 words in...
asked 1 hour ago -
1)Calculate the percent ionization of a
0.330 M solution of hypochlorous
acid.
% Ionization = %...
asked 1 hour ago -
1a) How many grams of K2SO4 are in 250mL
of 0.11 M K2SO4 solution?
_____ g...
asked 57 minutes ago -
The vapor pressure of a solution containing 38.7 g glycerin
(C3H8O3) in 146.2 g ethanol (C2H5OH)...
asked 1 hour ago -
A physics major is cooking breakfast when he notices that the
frictional force between the steel...
asked 1 hour ago