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Pad 1:58 PM * 51% --|- Objectives. Learn how to enhance the datapath and control for...
Question 4: Single Cycle Datapath Control (15 points) We wish to add the hardware support for a special R-type instruction jlr Jump and Link Register) to the single-cycle datapath below. Though this is an R-type instruction, but it is a special one that has the opcode being 000001 (instead of 000000), so the control unit will be able to differentiate this jlr instruction from the other R-type instructions and generate a special set of controls for this instruction. Opcode rs...
Part A: We wish to add the datapath parts and control needed to implement the jal (jump and link) instruction. Show the additions to the datapath and control lines of the figure enclosed (Figure 1 below) needed to implement these instructions in the multicycle datapath. There are multiple solutions; choose the solution that minimizes the number of clock cycles for the jal instruction. Part B: Show the additions to the finite state machine of Figure 2 below to implement the...
4. (10 pts) The following MIPS single-cycle datapath cannot perform Divide instruction. Indicate any changes to the datapath that must be done in order to support Div instruction, e.g., adding extra wires, extra logic gates, extra registers, etc. Do your modification on the following figure if necessary, and show the dataflow for this instruction using dash lines on the modified figure. Also show the values of the corresponding control signals in the following table and add new control signals to...
How would the multicycle MIPS design support the jr instruction? Show the machine code format and your solution should describe any new datapath features and control changes to the finite-state diagram below (this may include adding new states). Information for problem1 0 Instruction Fetch 1 Decode/Register Fetch 2 Address Calculation 3 Memory Read 4 Write-back Step 5 Memory Write 6 R-execution 7 R-completion 8 Branch completion 9 Jump completion O Mem Read ALUSelA 0 ALUSelB 01 lorD 0 ALUOp 00...
The answer to the table given by teacher is: RegDst-0 Jump-x Branch-1 MemRead-1 MemtoReg-x ALUop-1 MemWrite-x ALUSrc-1 (not sure about this one, please give your answer) RegWrite-x x means the signal cannot be set in this instruction. Could you explain the answer in details? 5. (35 points) We wish to add the single cycle datapath and control. Add an a new instruction im Gump memory) to page. This necessary datapaths and control signals to the attached figure on next new...