![5. (35 points) We wish to add the single cycle datapath and control. Add an a new instruction im Gump memory) to page. This necessary datapaths and control signals to the attached figure on next new jump instruction bm SI, S2, 100 writes PC with the value in memory location 0, i.e., PC (next PC)+memory [$2-100]. The format is the same as lw except that ri field is not used. Give control values of all the control lines for jm. Add more control lines if necessary RegDst Jump Branch MemRead T MemtoRe Reg Write ALUo Mem Write ALUSrc](http://img.homeworklib.com/questions/3131a410-cfac-11ea-b698-15b2fa593e6c.png?x-oss-process=image/resize,w_560)
The answer to the table given by teacher is:
RegDst-0
Jump-x
Branch-1
MemRead-1
MemtoReg-x
ALUop-1
MemWrite-x
ALUSrc-1 (not sure about this one, please give your answer)
RegWrite-x
x means the signal cannot be set in this instruction.
Could you explain the answer in details?
Homework Answers
In the image, for jump instruction address provided as jump
address[31 0].
This states destination register is 0
So RegDst-0
-------------------------------------------------------------------------------------
Jump register value will be depend on label or branch. Hence it may
have any value.
So Jump - x
------------------------------------------------------------------------------------------
Branch -> 1
Activating the branch register to 1 to allow execute jmp
instruction.
---------------------------------------------------------------------------------
MemRead -> 1
To jump from one branch to next branch, so need to write the data
from one brach to
next branch. So activate MemRead register to 1.
---------------------------------------------------------------------------------------
ALUop -> 1
This says the alu operations carry on while executing jmp
instruction.
----------------------------------------------------------------------------------------
MemWrite
Writing into memory is depend on instructions. So it may be any
value. Hence it is x. (no-operation)
---------------------------------------------------------------------------------------------
ALUSrc - 1
Yes, it is correct since logical operations need to be done.
-----------------------------------------------------------------------------------
RegWrite -> x
Only reading is required not Regwrite, so no operation.
Add Answer to:
The answer to the table given by teacher is:
RegDst-0
Jump-x
Branch-1
MemRead-1
MemtoReg-x
ALUop-1
MemWrite-x...
*For a clearer view of the datapath* Answer choices for all Consider the MIPS single cycle...
*For a clearer view of the datapath*
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Show the machine code format and your solution should describe any
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*For a clearer view of the datapath*
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Consider the MIPS single cycle datapath shown below. Select the correct control signals that will be generated by the control unit for the following instruction: andi $t0,$t1,4 Instruction (25-01 Shin Jump address (31-0) - left 2) 28 PC +4 [31-28) XCS result left 2 RegDst Jump Branch MemRead Instruction (31-26] MemtoReg Control ALUOP MemWrite ALUSrc RegWrite Instruction (25-21] PC Read address Read register 1 Read Instruction (20-16] Read data...
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How would the multicycle MIPS design support the jr instruction?
Show the machine code format and your solution should describe any
new datapath features and control changes to the finite-state
diagram below (this may include adding new states).
Information for problem1 0 Instruction Fetch 1 Decode/Register Fetch 2 Address Calculation 3 Memory Read 4 Write-back Step 5 Memory Write 6 R-execution 7 R-completion 8 Branch completion 9 Jump completion O Mem Read ALUSelA 0 ALUSelB 01 lorD 0 ALUOp 00...
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