2. Here is a series of addresses in hexadecimal 20(w), 3C(r), 10(r), 16(w), 20(r), 04(w), 28(r),...
1. A cache holds 64 words where each word is 4 bytes. Assume a 32 bit address. There are four different caches a. A direct-mapped cache with block size = 16 words b. 2-way set-associative cache with block size = 8 words c. 4-way set-associative cache with block size=4 words d. A fully associative cache with block size = 16 words. Complete the table for each cache. Cache a Cache be Cache Cache de 16 Number of bits needed for...
Here is a series of address references given as word addresses: 2, 3, 11, 16, 21, 13, 64, 48, 19, 11, 3, 22, 4, 27, 6, and 11. Using this references, show the hits and misses and the final cache contents for a two-way set-associative cache with one-word blocks and a total size of 16 words. Assume LRU replacements.
Using the sequences of 32-bit memory read references, given as word addresses in the following table: 6 214 175 214 6 84 65 174 64 105 85 215 For each of these read accesses, identify the binary address, the tag, the index, and whether it experiences a hit or a miss, for each of the following cache configurations. Assume the cache is initially empty. A direct-mapped cache with 16 one-word blocks. A direct-mapped cache with two-word blocks and a total...
2. A computer uses a memory with addresses of 8 bits. (What's the size of the MM?) This computer has a 16-byte cache with 4 bytes per block. (How many blocks in the cache?) The computer accesses a number of memory locations throughout the course of running a program. Suppose this computer uses direct-mapped cache. a. What's the format of a memory address as seen by the cache ? Tag ? bits Block ? bits Offset ? bits b. The...
For these problems, words are assumed to be 4 bytes, and the references are word-addresses. Thus, the words in memory are located in word-addresses 0, 1, 2, ... As a comparison, note that byte-addresses for words are multiples of 4. Thus, the byte-addresses for words are 0, 4, 8, 12,.... Note that the caches have a cache-line of two-words. We can write a 2-word block as follows (0,1), (2,3), etc are blocks 0, 1, ... Problem B (1 pts). Assume...
Caches are important to providing a high-performance memory hierarchy to processors. Below is a list of memory address references, given as word addresses (in decimal, the byte-offset bits have been excluded from addresses). 1, 4, 8, 5, 20, 17, 4, 56, 9, 10, 43, 5, 6, 9, 17 For each of these references, identify the binary address, the tag, and the index given a direct-mapped cache with two-word blocks (two words per block) and a total size of 8 blocks....
Here is a series of address references given as word addresses: 1, 4, 8, 5, 20, 17, 19, 56, 9, 11, 4, 43, 5, 6, 9, 17. For each of the following cache design, label each reference as a hit or a miss and show the final contents of the cache. Assume the caches are initially empty. - Direct mapped with four-word blocks and total size of 16 words.
Here is a series of address references given as word addresses: 2, 3, 11, 16, 21, 13, 64, 48, 19, 11, 3, 22, 4, 27, 6, and 11. Using this references, show the hits and misses and the final cache contents for direct-mapped cache with one-word blocks and a total size of 16 words.
Consider a memory hierarchy using one of the three organization for main memory shown in a figure below. Assume that the cache block size is 32 words, That the width of organization b is 4 words, and that the number of banks in organization c is 2. If the main memory latency for a new access is 10 cycles, sending address time is 1 cycle and the transfer time is 1 cycle, What are the miss penalties for each of...
A short program loop goes through a 16 kB array one word at a time, reads a number from the array, adds a random number, and stores the result in the corresponding entry in another array that is located in the memory immediately following the first array. An outer loop repeats the above operation 100 times. The 64-bit processor, operating at a clock frequency of 4 GHz, is pipelined, has 48 address lines, three levels of caches with a 64...