Question

EE 210 Digital Logic Experiment 3 - Basic Combinational Logic: Adjacency Tester- Simulation only. In this experiment, the student will design and simulate a minimal AND, OR and INVERTER circuit, with 4 input variables A, B, C, and D, and output F, that will produce a logic 1 output whenever two adjacent input variables are 1s. In this context, the A and D variables are also treated as being adjacent variables. See the partially filled-in Truth Table below, for more details. As a second step the student is to design the same logic circuit using an all-NAND realization, and to show that it gives the same results in simulation. Truth Table: 0 0 0 0 Procedure: The student is required to complete the truth table above, and to minimize the sum-of-product (SOP) expression from the truth table, using Karnaugh Maps; draw the simulated circuit diag for the AND-OR-INV implementation, and test its behavior in simulation. Next the student w show the All-NAND simulated circuit diagram for the system described, and show that it

Answer 1

Using karnaugh Maps: we can easily minimize this Sum-of-products: expression here F = Sigma M(3, 6, 7, 9, 11, 12, 13, 14, 15) = A^bar B^bar CD + A^bar B C D^bar + A^bar B C D + A B^bar C^bar D + A B^bar C D + A B C^bar D^bar + A B C^bar D + A B C D^bar + A B C D F = AB + CD + AD + BC We can implement this using AND and OR gates: \r\n Using AND is OR gate: Using NAND gates: F = (AB + BC) + (CD + AD) ^bar = AB + BC^bar midddot (CD + AD) ^bar^bar = AB^bar middot CD^bar middot BC^bar middot AD^bar^bar