Question

*in SystemVerilog

Problem1: 1) Study the clock divider lecture. 2) Implement the following designs in Systemverilog and simulate the SV design with a simulator a) Divide by 8 with 50% Duty Cycle b) Divided by 5 with 50% Duty Cycle

Answer 1

1: Divide by 5 clock

module clk_divn(clk,reset, clk_out);

input clk;

input reset;

output clk_out;

reg [2:0] pos_count, neg_count;

wire [2:0] r_nxt;

always @(posedge clk)

if (reset)

pos_count <=0;

else if (pos_count ==4) pos_count <= 0;

else pos_count<= pos_count +1;

always @(negedge clk)

if (reset)

neg_count <=0;

else if (neg_count ==4) neg_count <= 0;

else neg_count<= neg_count +1;

assign clk_out = ((pos_count > (5>>1)) | (neg_count > (5>>1)));

endmodule

2 : DIVIDE by 8 circuit verilog code

module clk_div (clk,reset, clk_out);

input clk;

input reset;

output clk_out;

reg [2:0] r_reg;

wire [2:0] r_nxt;

reg clk_track;

always @(posedge clk or posedge reset)

begin

if (reset)

begin

r_reg <= 0;

clk_track <= 1'b0;

end

else if (r_nxt == 3'b100)

begin

r_reg <= 0;

clk_track <= ~clk_track;

end

else

r_reg <= r_nxt;

end

assign r_nxt = r_reg+1;

assign clk_out = clk_track;

endmodule