01. Consider the stagevise single cycle CPU with the circuit as given on the attached sheet....
1. Assume that individual stages of the datapath have the following latencies: IF ID EX MEM WB 250 ps 350 ps 150 ps 300 ps 200 ps Also, assume that instructions executed by the processor are broken down as follows: alu beq lw sw 45% 20% 20% 15% What is the total latency of an ?w instruction in a pipelined and non-pipelined processor? Instead of a single-cycle organization, we can use a multi-cycle organization where each instruction takes multiple cycles...
6. Consider a datapath similar to the one in figure below, but for a processor that only has one type of instruction: unconditional PC-relative branch. What would the cycle time be for this datapath? PCSrc Add ALU Add result Shift +( left 2 Read register 1 ALUSrc, 4 ALU operation PCRead PC-address Read data 1 Registers Read data 2 MemWrite Zero ALU ALU-I Address MemtoReg Instruction register 2 Instruction | Write Read data-M register Write Lu memory Write Data data...
A particular (fictional) CPU has the following internal units and timings: 1. IFD: Instruction fetch + decode : 160 ps 2. RR: Register read 80 ps 3. ALU: 240 ps 4. MA : memory access: 160 ps (assuming cache) 5. RW : register write : 80 ps There are 5 basic instruction types: 1. LOAD : IFD+RR+ALU+MA+RW 720 ps 2. STORE: IFD+RR+ALU+MA : 640 ps 3. ARITHMETIC: IFD+RR+ALU+RW : 560 4. BRANCH: IFD+RR+ALU : 480 ps 5. MEMOP: IFD+RR+MA+ALU+MA :...
CASE II AziTech is considering the design of a new CPU for its new model of computer systems for 2021. It is considering choosing between two (2) CPU (CPUA and CPUB) implementations based on their performance. Both CPU are expected to have the same instruction set architecture. CPUA has a clock cycle time of 60 ns and CPUB has a clock cycle time of 75 ns. The same number of a particular instruction type is expected to be executed on...
Modify the circuit to support a MFCC instruction. MFCC Rd instruction: Move From Condition Codes MFCC copies into the four rightmost bits of Rd the values of the ALU signals Carry (C), Overflow (O), Zero (Z) and Negative (N) as they were set by the previous R- type instruction. The remaining 28 bits of Rd are set to zero. Describe the changes and additions needed for the single-cycle MIPS processor datapath and control to support this instruction. Hints: 1) MFCC...