Question

Modify the circuit to support a MFCC instruction.

MFCC Rd instruction: Move From Condition Codes
MFCC copies into the four rightmost bits of Rd the values of the ALU signals Carry (C), Overflow (O), Zero (Z) and Negative (N) as they were set by the previous R- type instruction. The remaining 28 bits of Rd are set to zero.

Describe the changes and additions needed for the single-cycle MIPS processor datapath and control to support this instruction.

Hints:
1) MFCC is an I-type instruction.
2) The control unit produces a signal called RType which is set to 1 if the decoded instruction is any R-type instruction and 0 otherwise.
3) The control unit produces a signal called MFCC which is set to 1 if the decoded instruction is MFCC and 0 otherwise.
4) The four signals Carry (C), Overflow (O), Zero (Z) and Negative (N), come from the ALU. N indicates if the value coming out of the ALU is negative.
5) Since MFCC gets the information from the previous R-type instruction, this means that the ALU signals must be latched in flip-flops by R-type instructions so they can be used by MFCC.

Instruction (25-0 Jump address [31-0 Shift left 2 26 28 PC+4 [31-28 Add ALU Addresut Shift left 2/ RegDst Jump Branch MemRead Instruction [31- ControlALUOp MemtoReg MemWrite ALUSIC RegWrite Instruction [25-21) Read register 1 Read data Read address PC Instruction [20-16] Read register 2 Zero ALU ALU Instruction 31-0 Instruction Address Read data Write register data 2 Read result Instruction [15-11 memory Write data Registers Write Data data memory Instruction [15-0 16 Sign 32 ALU extend control Instruction (5-0 Modify circuits, Highlight data paths Show all control signals Do not break earlier functionality

Answer 1

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