Question

Problem 2 Create in Quartus a 4-bit circular shift register with 4 types of shifting: • Left Shift • Right Shift • Load Input • Keep Value You may use your programming of choice to implement and simulate. Please turn in the simulation and a description of what is going on in the simulation. Notes: • Late submissions will not be accepted Honor pledge applies

Answer 1

ans............

1. Left & Right Shift :

library ieee;

use ieee.std_logic_1164.all;

use ieee.numeric_std.all;               -- Needed for shifts

entity example_shift is

end example_shift;

architecture behave of example_shift is

  signal r_Shift1     : std_logic_vector(3 downto 0) := "1000";

  signal r_Unsigned_L : unsigned(3 downto 0)         := "0000";

  signal r_Unsigned_R : unsigned(3 downto 0)         := "0000";

  signal r_Signed_L   : signed(3 downto 0)           := "0000";

  signal r_Signed_R   : signed(3 downto 0)           := "0000";

   

begin

  process is

  begin

    -- Left Shift

    r_Unsigned_L <= shift_left(unsigned(r_Shift1), 1);

    r_Signed_L   <= shift_left(signed(r_Shift1), 1);

     

    -- Right Shift

    r_Unsigned_R <= shift_right(unsigned(r_Shift1), 2);

    r_Signed_R   <= shift_right(signed(r_Shift1), 2);

    wait for 100 ns;

  end process;

end architecture behave;

3. Load Input & Keep value

signal Input_Delay : unsigned(3 downto 0);

  

process (clock)

begin

  if rising_edge(clock) then

    -- Create a delayed version of signal Input

    Input_Delay    <= shift_left(Input_Delay, 1);

    Input_Delay(0) <= Input;

    -- FYI: Same Code not using Shift Operator:

    Input_Delay(1) <= Input_Delay(0);

    Input_Delay(2) <= Input_Delay(1);

    Input_Delay(3) <= Input_Delay(2);

    Input_Delay(0) <= Input;

  

    if Input_Delay(3) = '1' then