a)
or instruction will make bitwise OR operation between the 2 operands
given ax is FA 75 and next operand is fff0
ax in binary is 1111 1010 0111 0101
fff0 in binary is 1111 1111 1111 0000
Hence or operation of the both operands is 1111 1010 0111 0000
which is FA70 in hexa decimal
Hence After execution of the instruction
AX : FA70h
SF : 1 (as the MSB of the result is 1 it indicates negative number)
ZF : 0 (as the result is non zero)
b)
TEST instruction performs a bitwise AND on two operands
it sets the flags CF and OF to zero, SF is set to the most significant bit of the result
If the result is 0, the ZF is set to 1
given ax is FA 75 and next operand is 0004
ax in binary is 1111 1010 0111 0101
0004 in binary is 0000 0000 0000 0100
Hence and operation of the both operands is 0000 0000 0000 0100
which is 0004 in hexa decimal
Hence After execution of the instruction
AX : 0004h
SF : 0 (as the MSB of the result is 0 it indicates positive number)
ZF : 0 (as the result is non zero)
c)
xor instruction performs a bitwise XOR on two operands
given dx is B6 A3 and next operand is 64C8
dx in binary is 1011 0110 1010 0011
64C8 in binary is 0110 0100 1100 1000
Hence xor operation of the both operands is 1101 0010 0110 1011
which is D26B in hexa decimal
Hence After execution of the instruction
AX : D26Bh
SF : 1 (as the MSB of the result is 1 it indicates negative number)
ZF : 0 (as the result is non zero)
d)
sal instruction performs shift arithimetic left on two operands
it will shift left by the number of bit positions equal to count and fill the vacted bit positions
on the right with 0's
given ax is A8 B5 and cl is 04 which means we have to shift A8 B5 by 4 positions left
ax in binary is 1010 1000 1011 0101
after shifting by 4 positions to left
ax will be 1000 1011 0101 0000
which is 8B50 in hexa decimal
Hence After execution of the instruction
AX : 8B50
CF : 0 (as the 4th bit shifted to the left in AX is 0 (in the nibble 1010))
e)
rcr instruction performs rotate right through carry on two operands
given ax is A8 B5 and count is 01 which means we have to rotate A8 B5 by 1 position right through carry.
ax in binary is 1010 1000 1011 0101
after rotating A8 B5 by 1 position right through carry.
ax will be 0101 0100 0101 1010
which is 545A in hexa decimal
Hence After execution of the instruction
AX : 545A
CF : 1 (as the 1st bit rotated to the right in AX is 1)
f)
sar instruction performs shift arithimetic right on two operands
it will shift right by the number of bit positions equal to count and fill the vacted bit positions
on the left with 0's
given BX is 8E BA and cl is 03 which means we have to shift 8E BA by 3 positions right
BX in binary is 1000 1110 1011 1010
after shifting by 3 positions to right
bx will be 0001 0001 1101 0111
which is 11D7 in hexa decimal
Hence After execution of the instruction
BX : 11D7
CF : 0 (as the 3rdbit shifted to the right in BX is 0 )
For each part of this problem, assume the "before" values when the given instruction is executed....
12. For each instruction in this question, assume that register contains the given contents before the instruction is executed. All values are Hex, Contents of the register (Before) al-coh Contents of the register (After) Instruction ZF CF OF SF | add al, 40h ;assume values are unsigned Int | add bh, 9Ah ;assume values are signed Int | add cl, 52h ;assume values are signed Int | add bh, 01h ;assume values are bh=66h cl=40h bh= the value from unsigned...
Moving to another question will save is response. Question 4 Assume that before the instruction is executed, the flags are CF=1, ZF=1 and SF=1 and the Registers have the values AL=OXAF, BL=0x75 CL=0x48 and DL=OXEA. What are the values of the flags after the instruction ADD AL, OxF4 executes? CF = ZF = SF = A Moving to another question will save this response.
b. A microprocessor has an instruction set that consists of 117 instructions, which need fetch, decode, read operand, execute, write and interrupt stages. Assume that as an average, each stage requires three micro- operations to complete. Also, assume that the control memory is N bits wide (i.e., control field bits + address selection field bits + address-one bits + address-two bits N bits). The control field bits are 15 and there are 15 flags to be monitored. i. How many...
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