Question

1. (30 pts) The pull up network (PUN) is provided for the CMOS logic gate below. 8 Voo Quo EL Pull Down Network a) (10 pts) Sketch the equivalent pull down network (PDN). b) (10 pts) If each transistor in the gate has a length of Lmin, select gate widths in microns) for each p-channel transistor based on best practice sizing principles and referenced to the minimum sized inverter in the technology. W OpA = Lim WOD = um WOpB = um WpE = um Wpc =

Answer 1

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1. The pull Apage-No-1 the CMOS down network for is as shown below: pVDD VDD Qp B . QpC Dan apo tk Qpe B tok QNA NA Die Pull-Down HK QNc NetworĒ GND' fig: cmos Logic Смо

WWA UNLI No-2 repage-No-2 b) By taking the minimum sized inverter, the sizes of the P-channel transistors can be selected for best sizing - here, the gate length is fixed (Lmin), the gate widths should be selected by considering the worst case of operation at which the maximum delay is produced - For the p-channel transistors in the above (-Mos logic the worst case is when E, D, C, B input transistors QPE, APD, Qpe, apes are 'ONE - The crerall resistance offered by the he path should be Equel to the resistance offered by a reference CMOS. - There fore RPE=RP=RP = RPB = REI where RI = resistance of reference CMOS inverterria

a page-no-3 »RE, RD, Rc and RB are the resistances offered by QPE, QPD PP, and QPB Now, RPE+ Rppt Ret RPB = PP I otok PAPETRPB = RpZ The delay to CXR estat → Resistance of MOSFÉT Rd wh o There 'L' is fixed (=) R2 1 = td / ALLOW - Let "halt be the width of the reference inventer p-channel MOSFET. here! RPE 2 Repa) Wit = 4X(WI) sem RP p = REI / ha hapo = 4x (KII), um RPc = RPI = Wasc = ux (WI) um RP B= Rp 1 - Waps = ux (WI) um Now From the figure, here . Rom Now, PA= BB+ Rpc = 2 RP I = RP I/ ū72 byla 26 WI) en