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3. Consider the circuit in the Problem #2 again. Assume all transistors are in saturation and Vdd is sufficiently high to keeVdd Vout M1 M2H . M13 Ms and M12 M15 / M6 Gnd

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Q.3 Ane: 7,5 50/40 for deg fiks-Mall. JPC14065) a) Do = (veg Panel J Q ( 1+0.012] :) 0.444= [vsg. Vinpl >|4500 = [(a)m - smug(3) Tas axmp*Drax (ugevanj®(tdks) z (vag- Vin) ac sgomv. (tng - Van) g = 220 - 300= 690m V Iso 12 Xpx W) og (Veg - Yn) {1+28% ( 6 ) . . . _106 СТ, О.04 x 120.5 Гој го ак) Гtos - Cog - Co4 D w) Coat mg тоа «лә» Г», «» (%. )) - загаль о-ax0-2хло“) Тэ

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