library ieee;
use ieee.std_logic_1164.all;
entity oddno is
port(a: in std_logic_vector(2 downto 0);
y: out std_logic_vector(6 downto 0));
end oddno;
architecture beh of oddno is
begin
process(a)
begin
case a is
when "000" =>
y<= "0110000"; -- format for show E in seven segment display
when "001" => -- odd no.
y<= "1001111"; -- format for show 1 in seven segment display
when "010" =>
y<= "0110000"; -- format for show E in seven segment display
when "011" => -- odd no.
y<= "0000110"; -- format for show 3 in seven segment display
when "100" =>
y<= "0110000"; -- format for show E in seven segment display
when "101" =>
y<= "0100100"; -- format for show 5 in seven segment display
when "110" =>
y<= "0110000"; -- format for show E in seven segment display
when "111" =>
y<= "0001111"; -- format for show 7 in seven segment display
when others=>
y<= "0110000"; -- format for show E in seven segment display
end case;
end process;
end beh;
Type down the code so I can copy it directly please. Dont write on papers or...
please dont write the VHDL code on paper just copy and paste it from the program Q1 K101 Fig. 2 (b) Use the structural design style to write the VHDL code (entity and architecture) to describe the circuit in Fig. 2 if the entity of the JK flip-flop is as shown below: entity JKYT is port( Q. NO: out atd logies CLK, CLR, J, K instd_logie); and JKPF; (5 marks)
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Jubail University College Computer Science & Engineering Department Assessmen Assignment Course Code CS120/C5101 t Type: 1 Semester: 403 Course Title Programming Submission 27-06-2020 Total Points 8 Date Submission Instructions: • This is an individual assignment. • Please submit your program (Java fle) in Blackboard. You can create one java project, named as Assignment1_id and add separate java file for each question. You can name your javá files as 01.02.... etc. • Make sure that you include your student ID name...
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