Question

please dont write the VHDL code on paper just copy and paste it from the program

Q1 K101 Fig. 2 (b) Use the structural design style to write the VHDL code (entity and architecture) to describe the circuit in Fig. 2 if the entity of the JK flip-flop is as shown below: entity JKYT is port( Q. NO: out atd logies CLK, CLR, J, K instd_logie); and JKPF; (5 marks)

Answer 1

vhdl code for jk flip flop module:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_arith.all;

entity JKFF is
Port ( CLR,CLK,J,K : in STD_LOGIC;
Q,NQ : out STD_LOGIC);
end JKFF;

architecture Behavioral of JKFF is
begin
process(CLK)
variable temp:std_logic;
begin
if (CLR='1') then
temp:='0';
elsif(clk='1' and clk'event) then
if(J='0' and K='0')then
temp:= temp;
elsif(J='0' and K='1') then
temp:= '0';
elsif(J='1' and K='0') then
temp:= '1';
elsif(J='1' and K='1') then
temp:= not temp;
end if;
end if;
Q<=temp;
NQ<=not temp;
end process;
end Behavioral;

Portmapping according to the given circuit by taking the JKFF as component:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity logic_circuit is
Port ( CLK,CLR : in STD_LOGIC;
Q : out STD_LOGIC);
end logic_circuit;

architecture Behavioral of logic_circuit is
component JKFF is
Port ( CLR,CLK,J,K : in STD_LOGIC;
Q,NQ : out STD_LOGIC);
end component JKFF;

begin
L0: JKFF port map(Q0,NQ0,CLR,CLK,NQ1,1);
L1:JKFF port map(Q1,NQ1,CLR,CLK,1,NQ0);

end Behavioral;