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a. Write a Verilog code that represents the following circuit in Figure Q4 in ANY coding...
Please solve the problems from 2_5 Digital system Problem 2 Design a combinational circuit with inputs a, b, c, d and outputs w, x, y, z. Assume that the inputs a, b, c d represent a 4-bit signed number (2s complement). The output is also a signed number in 2s complement which is 5 greater than the input if the input is less than 2, and is 2 less than the input if the input is greater than or equal...
1- Please answer all the question 2- with clear handwriting Thank you, 3. Design a combinational circuit with inputs a, b, c, d and outputs w, z, y, z, where the input and output both represent a signed numbers (2s complement). The output is 7 less than the input, if the input is positive, or zero. If the input is negative, the output is 3 greater than the input. 7. Use the Boolean functions developed in problem #3 to create...
Write a testbench for use in Quartus' ModelSim Altera in verilog for the following code of a 4x16 register: module regFile4x16 (input clk, input write, input [2:0] wrAddr, input [15:0] wrData, input [2:0] rdAddrA, output [15:0] rdDataA, input [2:0] rdAddrB, output [15:0] rdDataB); reg [15:0] reg0, reg1, reg2, reg3; assign rdDataA = rdAddrA == 0 ? reg0 : rdAddrA == 1 ? reg1 : rdAddrA == 2 ? reg2 : rdAddrA == 3...
Using Verilog, write a simulation code that shows the function g(w, x, y, z) = wxyz + w’x’y’z+w’x’yz’+w’xy’z’+wx’y’z’ using a 4 to 16 decoder that is built with two 3 to 8 decoders. The 3 to 8 source code I'm using is: module Dec3to8( input[2:0] A, input E, output[7:0] D ); assign D[0] = E & ~A[2] & ~A[1] & ~A[0]; assign D[1] = E & ~A[2] & ~A[1] & A[0]; assign D[2]...
(a) Given a circuit in Figure Q4(a): (1) State the condition for maximum average power transfer to the load impedance. Z (2 marks) (1) Determine the load impedance, Z (4 marks) (in) Find the maximum average power (5 marks) Lt mm JI R RE 492 120° A 20 C. 70.502 W ZL 1 Figure Q4(a) An air conditioner operates at 240V... at a frequency of 60 Hz. It absorbs an average power of 9 kW at a lagging power factor,...
Write a VERILOG simulation code for a 3 to 8 decoder and a simulation code for a 4 to 16 decoder using two 3 to 8 decoders. The code used for 3 to 8 decoder: Code used for 4 to 16 decoder: Need help with simulation code. 22 module Dec3to8 ( 23 input [2:0 A input E output [7:0] D 24 25 26 27 E &A[2]& 28 assign D[0] A[1 A[0] E &A[2] &A[1] assign D[1] & A[0] 29 E...
Please solve the problems from 1_5 Digital system Complete the following homework problems. Show all work (making sure it is legible) and circle all answers for clarity Problem 1 w3 w4 B w1 a) Determine Boolean functions for intermediate outputs w,w2,w3, and w4 as well as the output signals X and Y. b) Construct a truth table showing the intermediate outputs wl,w2,w3, and w4 as well as the output signals X and Y c) Use K-maps to find simplified expressions...
5.28 The Verilog code in Figure P5.9 represents a 3-bit linear-feedback shift register (LFSR) This type of circuit generates a counting sequence of pseudo-random numbers that repeats after 2" - 1 clock cycles, where n is the number of flip-flops in the LFSR. Synthesize a circuit to implement the LFSR in a chip. Draw a diagram of the circuit. Simulate the circuit's behavior by loading the pattern 001 into the LFSR and then enabling the register to count. What is...
Please solve the problems from 7_8 Digital system please just answer 7_8 thank you 1 Chapter 3 problems 1. Minimize the following Boolean functions into sum-of-products form using a K-majp (a) F(z, y, ;) = Σ(0, 1, 2, 3, 5, 6) (b) F(a,b, c) 20,1,4,5,7) (c) F(z,y,2)s Σ(1.3.5.7) (d) F(a, b, c) 0,4,7) 2. Minimze the following Boolean functions into sum-of-products form using a K-map (b) Fla,b,c)= Π(0.1.4.5.7) (c) F(z, y,z)= Π(2,4,6) (d) F(a,b,c)-Π(1,2,3,4) 3. Minimize the following Boolean functions...
Please solve Q1 and Q2 Complete the following homework problems. Show all work (making answers for clarity sure it is legible) and circle all Problem 1 w3 X A w4 w1 C D Y w2 Determine Boolean functions for intermediate outputs wl,w2,w3, and w4 as well as the output signals X and Y. b) a) Construct a truth table showing the intermediate outputs wl,w2,w3, and w4 as well as the output signals X and Y Use K-maps to find simplified...