Question

3. It is desired to design an 8x2 (8 words each 2 bit long) NAND-based ROM that serves as a lookup table to implement a full-adder. Represent the row decoder as a "block diagram" (you need to label the block clearly, # of inputs, # of outputs, etc...). Everything else needs to be circuit-designed

Answer 1

The truth table for full adder

B2	B1	B0	S	C
0	0	0	0	0
0	0	1	1	0
0	1	0	1	0
0	1	1	0	1
1	0	0	1	0
1	0	1	0	1
1	1	0	0	1
1	1	1	1	1

The 2bit result ( S C) has to be stored in the ROM which can be represented as follows using NAND logic.

A decoder should decode each line.

Vdd R1 R2 R3 R4 R5 R6 R7 R8

When R1 = 0 first word will be selected, R2 second word will be selected etc.

We have to design a decoder that selects these line depending on the input of the full adder

Truth Table for Decoder

B2	B1	B0	R1	R2	R3	R4	R5	R6	R7	R8
0	0	0	0	1	1	1	1	1	1	1
0	0	1	1	0	1	1	1	1	1	1
0	1	0	1	1	0	1	1	1	1	1
0	1	1	1	1	1	0	1	1	1	1
1	0	0	1	1	1	1	0	1	1	1
1	0	1	1	1	1	1	1	0	1	1
1	1	0	1	1	1	1	1	1	0	1
1	1	1	1	1	1	1	1	1	1	0

The final circuit

R1 R2 R3 R4 R5 R6 R7 R8 B2 B1 3x8 Decoder B0

Vdd B2 B1 3x8 Decoder BO