Question

1. There are three fundamental I/O strategies used in microcontroller systems, namely: polling, interrupt the driven and DMA.

a) Explain each of these strategies you should illustrate your explanation with examples of use and comparison of the relative cost and complexity of each strategy.

A microcontroller is to be used to drive a video display. The display has a resolution of 512 *512 pixels, a color depth of 8 bits/ pixel and a refresh rate has 30HZ.

b) Determine the data rate (in bits per second) required to drive this display.

c) suggest the most appropriate I/O strategy for this application.

Answer 1

a)

The three I/O strategies used in Microcontroller systems are explained as follows-

1.Polling

It is a method where the CPU periodically keep looking at the I/O device to check whether the device is ready to transmit data by checking its status bit(or bits).It is a software driven method of I/o communication.

For example-

              LDA #150 ;Loads into accumulator the data at location 150

              STA 80 ;Stores that data into memory location 80

CHECK: IN 101 ;The status bit of our I/O device at port location 101 is input

             AND #1 ;The status bit(or, for status word last bit) is checked for 1

             JZ CHECK ;If it is not 1, jump to CHECK

             LDA (80) ;Load data from location 80 into Accumulator

             OUT 100 ;Send Accumulator data to output port 100

             LDA 80 ;Load into accumulator

             ADD #1 ;Increment 1 to goto next location

             STA 80 ;Again store it in location 80

             SUB #200 ;Subtact from 200 to check if the result is 0

             JNZ CHECK

In the above example, we want to transfer 50 words of data starting at location 150 to an output device at address 100 whose status is checked by the status bit at location 101 in a loop(CHECK) and when it finds that bit(or group of bits with last bit) as 1 it transfers the Memory data.

To see its inefficiency, if our CPU is 2GHz and each instruction takes 2 cycles ;then, 3*2=6 cycles,i.e. 6/(2*10^9)=~10^-9 sec are wasted by CPU to compute polling loop and if I/O device has speed of 1000 bytes per second ;it takes 10^-3 second for one byte.So, CPU executes polling loop about 10^6 times waiting for device to be ready.

Hence, it can be concluded that the system is inefficient though not complex and the relative cost is less.

2.Interrupt Driven I/O

This is a Hardware based I/O communication method wherein the peripheral interrupts the CPU from its usual flow through programmed instructions.In the program memory a set of interrupt service subroutines(ISR) are already written which contains the instructions to be executed when a particular type of interrupt is encountered. When the interrupt is detected the processor stops executing its present instruction and jumps to execute the particular subroutine and, once completed, returns to the previous state.

There are various interrupts designated on the basis of their priority.A higher priority interrupt, if executing currently can't be interrupted by a lower priority interrupt, which is dealt with only after the higher priority interrupt is executed completely.Some Hardware interrupts are non-maskable in nature which means those can't be avoided or delayed and are dealt immediately.

The hardware based interrupt is more complex as compared to polling as complex programming and scheduling of interrupt is to be taken care of .The cost is less as those are already present in the CPU functionality and no extra cost is involved.

3.DMA

In DMA, the peripheral has direct access to processor's Memory bus.It enables the peripheral,such as UART to transfer data directly to or from memory without having processor's interference for each byte/word transfer.The DMA has the advantage of higher throughput than any other methods mentioned before.

In a typical DMA transfer,an event notifies a device called DMA controller that data needs to be transferred to memory by sending an incoming signal.The DMA controller then sends a "DMA request" signal to the CPU,asking permission to use the bus.The CPU completes its current activity and sends a "DMA acknowledge signal" to the DMA controller.Now the DMA control has direct access to the memory which it uses to read and/or write data and control the signals.When the transfer is complete the DMA controller stops driving the busand takes back "DMA request" signal.The CPU then takes back "DMA Acknowledge" signal and resume control of bus.

The DMA mode of I/O is little complex and costly ;however, the speed of transfer and efficiency is more.

b)

Given:

Display resolution=512*512 pixels

color depth=8 bits/pixel

Refresh rate=30Hz

Data Rate required to drive the display ?

No. of bits for 512*512 pixels=512*512*8=20,97,152.

Rate of refresh=30 per second.

Hence Data rate(bits/sec) required=30*2097152=6,29,14,560 =7.5MBps(MegaByte persecond)

c)

The most appropriate I/O strategy for this application is DMA as high throughput of data is required here.