design a serial even parity generator, a binary sequence of arbitrary length will be presented to...
design a serial even parity generator, a binary sequence of arbitrary length will be presented to the partity generator circuit on input x. when a given bit is presented on input x, the corresponding even parity bit is to appear during the same clock cycle on output z. to indicate that a sequence is complete and that the circuit is to be initialized to receive another sequence, the input Y becomes 1 for one clock cycle.
draw the state diagram and derive the state table. then finally find a circuit implementation using sr flip flop and logic gates.
Homework Answers
We use excitation table of SR Flip Flop to formulate State Table.
State diagram is shown with three states.
|
PRESENT STATE |
INPUTs |
NEXT STATE |
OUTPUT |
SR FLIP FLOP INPUTs |
||||||
|
Q1 |
Q0 |
X |
Y |
Q1+ |
Q0+ |
Z |
S1 |
R1 |
S0 |
R0 |
|
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
X |
0 |
X |
|
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
X |
0 |
X |
|
0 |
0 |
1 |
0 |
0 |
1 |
0 |
0 |
X |
1 |
0 |
|
0 |
0 |
1 |
1 |
0 |
0 |
0 |
0 |
X |
0 |
X |
|
0 |
1 |
0 |
0 |
0 |
1 |
0 |
0 |
X |
X |
0 |
|
0 |
1 |
0 |
1 |
0 |
0 |
0 |
0 |
X |
0 |
1 |
|
0 |
1 |
1 |
0 |
1 |
0 |
1 |
1 |
0 |
0 |
1 |
|
0 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
X |
0 |
1 |
|
1 |
0 |
0 |
0 |
1 |
0 |
0 |
X |
0 |
0 |
X |
|
1 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
1 |
0 |
X |
|
1 |
0 |
1 |
0 |
0 |
1 |
0 |
0 |
1 |
1 |
0 |
|
1 |
0 |
1 |
1 |
0 |
0 |
0 |
0 |
1 |
0 |
X |
|
1 |
1 |
0 |
0 |
X |
X |
X |
X |
X |
X |
X |
|
1 |
1 |
0 |
1 |
X |
X |
X |
X |
X |
X |
X |
|
1 |
1 |
1 |
0 |
X |
X |
X |
X |
X |
X |
X |
|
1 |
1 |
1 |
1 |
X |
X |
X |
X |
X |
X |
X |
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