Question

(Don't do the simulation If you don't have LigoSim to simulate) I appreciate your efforts and time in advance!

1. a)Simulate and test a 1-bit full adder. Use 2-input exclusive OR gates to realize Sum. Use an SOP form to realize C_out

b) Simulate and test a 4-bit adder circuit using serially interconnected 1-bit full adder sub-circuits. The adder will be able to add 4 bit positive numbers and should be able to add 15 and 15 to get 30.

c) If each gate has a propagation delay of Dt, determine how long after the input signals are applied that it take before the output is ensured to be correct. Determine the worst case path and find an input signal combination will cause the worst case delay. For instance, if two numbers (A and B) are placed on the input lines at time=0, how long will it take to get the correct answer in the worst case scenario.

Answer 1

truth table for 1 -bit full adder

A         B          C_in     Sum     Carry

0          0          0          0          0

0          0          1          1          0

0          1          0          1          0

0          1          1          0          1

1          0          0          1          0

1          0          1          0          1

1          1          0          0          1

1          1          1          1          1

the circuit for 1-bit full adder is shown below:

the 4 bit adder circuit using the above 1 bit full adder is shown below:

since cout has the worst delay path

since

for Cout t be corrent we have to look for all the previous Carry generated

hence

Cout delay is

1 and gate + or gate each stage of ripple

hence 2delta per stage

hence for 4 stages, we have 8 Dt delay.

for Sum out. the last bit of sum has to go through all delays and carry generated in worst-case scenarios

hence the path will be 2 xor gate delay +3(and + or ) gate

since 3 carries will be generated

6+2=dtdelay

hence maximum delay will be 8 Dt