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Please; I need an answer only for part C; thanks a) Simulate and test a 1-bit...

Please; I need an answer only for part C; thanks

  1. a) Simulate and test a 1-bit full adder. Use 2-input exclusive OR gates to realize Sum. Use an SOP form to realize Cout (see the back page of this handout). Save the circuit. Save the schematic by using File|Export.

b) Simulate and test a 4-bit adder circuit using serially interconnected 1-bit full adder sub-circuits. The adder will be able to add 4 bit positive numbers and should be able to add 15 and 15 to get 30. Save the schematic by using File|Export.

c) If each gate has a propagation delay of ∆t, determine how long after the input signals are applied that it takes before the output is ensured to be correct. Determine the worst-case path and find an input signal combination will cause the worst-case delay. For instance, if two numbers (A and B) are placed on the input lines at time=0, how long will it take to get the correct answer in the worst-case scenario. Discuss any limitations of this design regarding how fast this circuit will be in computing results.

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