Question

Minimize and Simplify using the Array Technique

Code using Verilog

0/0 1/0 1/0 0/0 x/0 0/0 0/0 1/0 x/0 x/0 x/0 0 1 Minimize the number of states 2- Do the state assignments to minimize the IFL and OFL. 3- Complete the design of this state machine using JK flip-flops. 4 Code the state machine. 5- Write a test bench to simulate it. 6- Simulate it for different words.

Answer 1

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//JK Flip Flop Module verilog code

module jkff(rst,clk,j,k,q,qbar);

//Portlist

input rst,clk,j,k;

output reg q;

output qbar;

//Sequential Block and output logic

always@(posedge clk) begin

if(rst)

q <= 1'b0;

else begin

case({j,k})

2'b00 : q <= q;

2'b01 : q <= 1'b0;

2'b10 : q <= 1'b1;

2'b11 : q <= ~q;

endcase

end

end

//Output for Q bar

assign qbar = ~q;

endmodule

//FSM Verilog Code

module FSM(

//Portlist

input i,

input clk,rst,

output reg out

);

//internal wires

wire j1,k1,j0,k0,q1,q0,q1_bar,q0_bar;

//Instantiation of JK Flip Flop

jkff JK_0(rst,clk,j0,k0,q0,q0_bar);

jkff JK_1(rst,clk,j1,k1,q1,q1_bar);

//Internal State Parameters

parameter a = 4'b00,

b = 4'b01,

c = 4'b10,

d = 4'b11;

//State Declaration

reg [1:0]current_state;

//Combo Block for JK inputs, next state for JK

assign j1 = (i & current_state[0]);

assign k1 = ((~i) | current_state[0]);

assign j0 = (i ~^ current_state[1]); //xnor

assign k0 = 1;

//Current State Block

always@(*) begin

case({q1,q0})

2'b00 : current_state = a;

2'b01 : current_state = b;

2'b10 : current_state = c;

2'b11 : current_state = d;

default:current_state = a;

endcase

end

//Output logic Sequential Block

always@(posedge clk) begin

if(rst)

out <= 1'b0;

else begin

case(current_state)

d : begin

if(i)

out <= 1'b1;

else

out <= 1'b0;

end

default:out <= 1'b0;

endcase

end

end

endmodule

//Test Bench for FSM

module test;

reg i, clk,rst;

wire out;

//Instantiation of FSM

FSM FSM_INST(i,clk,rst,out);

always begin

#5 clk = 1'b0;

#5 clk = ~clk;

end

initial begin

@(posedge clk) rst =1'b1;

@(posedge clk) rst =1'b0;

i = 1'b0;

@(posedge clk) i = 1'b1;

@(posedge clk) i = 1'b1;

@(posedge clk) i = 1'b1;

@(posedge clk) i = 1'b1;

@(posedge clk) i = 1'b0;

@(posedge clk) i = 1'b1;

@(posedge clk) i = 1'b0;

@(posedge clk) i = 1'b1;

@(posedge clk) i = 1'b1;

@(posedge clk) i = 1'b0;

@(posedge clk) i = 1'b1;

@(posedge clk) i = 1'b1;

@(posedge clk) i = 1'b1;

@(posedge clk) i = 1'b0;

repeat(2)

@(posedge clk); $finish;

end

endmodule

//Simulation waveform

.-E-9-1 Search: test/FSM_INST/i test/FSM INST/clk test/FSM INSTIrst Sto Sto Sto 00 ◆ M-INST/current-state test/FSM INST/out /test/FSM-INST/)! /test/FSM INST/k1 test/FSM INSTO /test/FSM INST/kO test/FSM INST/ql test/FSM INST/qO test/FSM INST/q1 bar Sto St1 St1 St1 Sto Sto St1 0.18 ns ns Cursor 1 0.167 ns 0 ps to 192 ps test/FSM INSTA