Question

PCSrc Add ALU Add result Shift left 2 Read register 1Read Read register 2 Write register Write data RegWrite Read ALU operation MemWrite data 1 MemtoReg Zero ALU ALUAddresS data Instruction Registers Read Read Instruction MI IMI memory WriteData data memory 16 Sign- MemRead extend 3, (4 points) For question#2, in the datapath as shown in Fig. 1, assume that one of the following control signals has a stuch-at-0 fault, meaning that the signal is always 0, regardless of its intended value. Which instruction(s) for the following five instructions (I1-15) will fail (cannot be executed)? Or all instructions can be executed successfully? Please justify your answer II: add Ssl, Ss2, Ss3 12: 1w Ss4, 4(Ss4) 13: addi Ss5, St3, 8 14: beq Stl, St2, loop 15: sw St2, 6(Ss2) (a) MemtoReg (b) PCSrc (c) MemWrite (d) ALUSrc

Answer 1

(a)MemtoReg = 0 (only load word do write register after reading from memory)
add $s1,$s2,$s3 (it will work correctly because its MemtoReg =0)
lw $s4 ,4($s4) (it will not work correctly because its MemtoReg =1)
addi $s5 ,$t3,8 (it will work correctly because its MemtoReg =0)
beq $t1 ,$t2,loop (it will work correctly because its MemtoReg =X (don't care))
sw $t2 ,6($s2) (it will work correctly because its MemtoReg =X (don't care))

(b)PCSrc = 0 (only branch instructions need PC value to decide target address)
add $s1,$s2,$s3 (it will work correctly because its PCSrc =0)
lw $s4 ,4($s4) (it will work correctly because its PCSrc =0)
addi $s5 ,$t3,8 (it will work correctly because its PCSrc =0)
beq $t1 ,$t2,loop (it will not work correctly because its PCSrc =1)
sw $t2 ,6($s2) (it will work correctly because its PCSrc =0)

(c)MemWrite = 0 (only store word (sw) do memory write)
add $s1,$s2,$s3 (it will work correctly because its MemWrite =0)
lw $s4 ,4($s4) (it will work correctly because its MemWrite =0)
addi $s5 ,$t3,8 (it will work correctly because its MemWrite =0)
beq $t1 ,$t2,loop (it will work correctly because its MemWrite =0)
sw $t2 ,6($s2) (it will not work correctly because its MemWrite =1)

(d)ALUSrc = 0
add $s1,$s2,$s3 (it will work correctly because its ALUSrc =0)
lw $s4 ,4($s4) (it will not work correctly because its ALUSrc =1)
addi $s5 ,$t3,8 (it will not work correctly because its ALUSrc =1)
beq $t1 ,$t2,loop (it will work correctly because its ALUSrc =0)
sw $t2 ,6($s2) (it will not work correctly because its ALUSrc =1)