Question

Could you please give me the T-Flip Flop and also 4-bit Binary Ripple Counter VHDL structural code with testbench

Answer 1

--VHDL Code of T Flip Flop

library ieee;
use ieee.std_logic_1164.all;

entity tff is
   port (   clock   : in std_logic;  
       reset   : in std_logic;  
       T   : in std_logic;
       Q, QBAR   : out std_logic
   );
end tff;

architecture arch of tff is

signal qreg : std_logic:='0';

begin

process (clock)

begin

   if rising_edge(clock) then
  
       if (reset = '1') then

           qreg <= '0';

       else

           if (T = '1') then

               qreg <= not qreg;

           else

               qreg <= qreg;  

           end if;
       end if;
  
   end if;

end process;

Q <= qreg;

QBAR <= not qreg;

end arch;

----------------------------------------------------------------------------------------------------------------------------------------------------------

--Structural Model of ripple counter using T Flip Flop

library ieee;
use ieee.std_logic_1164.all;

entity ripple_count is

   port (   clock   : in std_logic;  
       reset   : in std_logic;  
       Q   : out std_logic_vector(3 downto 0)
   );
end ripple_count;

architecture arch of ripple_count is

component tff is
   port (   clock   : in std_logic;  
       reset   : in std_logic;  
       T   : in std_logic;
       Q, QBAR   : out std_logic
   );
end component;

signal s : std_logic_vector(2 downto 0);

begin

uut0 : tff port map (clock, reset, '1', Q(0), s(0));
uut1 : tff port map (s(0), reset, '1', Q(1), s(1));
uut2 : tff port map (s(1), reset, '1', Q(2), s(2));
uut3 : tff port map (s(2), reset, '1', Q(3), open);

end arch;

----------------------------------------------------------------------------------------------------------------------------------------------------------

--Test bench

library IEEE;
use IEEE.Std_logic_1164.all;
use IEEE.Numeric_Std.all;

entity ripple_count_tb is
end;

architecture bench of ripple_count_tb is

component ripple_count
   port (   clock   : in std_logic;  
       reset   : in std_logic;  
       Q   : out std_logic_vector(3 downto 0)
   );
end component;

signal clock: std_logic;
signal reset: std_logic;
signal Q: std_logic_vector(3 downto 0) ;
constant clock_period: time := 10 ns;

begin

uut: ripple_count port map ( clock => clock,
reset => reset,
Q => Q );

clock_gen: process
begin
  
clock <= '0';
wait for clock_period/2;
clock <= '1';
wait for clock_period/2;
  
end process;

stimulus: process
begin
reset <= '1';
wait for 2 * clock_period;
reset <= '0';
  
wait;
end process;

end;

---------------------------------------------------------------------------------------------------------------------------------------------------------------

--Simulation on ModelSim

E Wave File Edit View Add Format Tools Bookmarks Window Help Wave -Default Msgs ripple_ count tb/reset 1001 40000 1 2080594349 ps ripple counttb 0 ps to 274210 ps fclock 1252 AM rP ︿DAdyp 5/6/2019 O Type here to search