Question

#4

The accompanying circuit shows a 4-resistor biased JFET transistor Determine the values of Rp and Rs so that the Q-point is equal to, VDsq 10 V and IDg 5 mA . For the JFET take IDss = 10 mA, VP =-5 V and λ 0 . The circuit parameters are, R1-740 k, R2-22 1.85 ka, Rs-85 ㏀ and RL-3.5 ㏀. Take the power supply VDD 24 V 2- Vo R1 Vi R2 Signal generator 4-In reference to the circuit of problem # 2 ,what is the required maximum peak-to-pe am ak plitude [ vs(max)] of the signal generator, that will confine the FET operation into its saturation region? (Estimate and support your answer with a comm Vs (max) = Hint: draw Ip vs. VDs axis, mark the Triode-Saturation region boundary with its locus Place the Q-point and draw the ac load-line and consider the voltage swing and the constraints existing on VDs and-5 3 VGS0 and ID 10 mA.

Answer 1

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