Question

2. (20 pts.) Write the finite state machine (FSM) of the circuit shown below. Hint: In the given DEMUX below, S2 is the input signal, S1-Q1, s0-Q0 and there is a single output labeled as M. X100 FrO 113 1 NPUT IGartac Yemisc1o01

Answer 1

com2 irel Enable 91 com 001 FF1 010 om8 011 DEMUX 100o 101 com7 com5 110 com4 wire0 S2 S1 S0

timescale 1ns/1ps module demux(enable,s2,s1,s0,out) input sO,s1,s2enable; output reg [7:0 out, always @r) begin out=8 3boo1 out-8boo000010 3b010 out-8boo000100 3'bo11 :out-8b00001000; 3b100 out-8boo010000; 3b101 out-8b0o100000 3b110 out-8b01000000

module dfid,clk,rst,q) input d,clk,rst always @posedge clk or posedge rst) begin endmodule ++ top level circuit module fsm_circuit input xclk,output M wire qi,q0, wire1 wire0,d1,do; demux com1(1b1,x,q1,qo,w); or com2/wire1,wf1J,w[2],wl4]); or com3d1,wirel,W[7]); or com5(do,w[O),wireO) dff com6(d1,clk,ql); dff com7/dO,clk,qo) xor com8(M,qi,qo);