At this point in your Digital Logic career, an assignment comes where you need to put all your knowledge of J-K flip-flops, counters and shift registers together and design, build and test a circuit that will detect a "101" pattern in a serial bit stream and output a
HIGH level coincident with the final "1" in the pattern, Using A Qty. of 2, J-K Flip-Flops
1) Create a State diagram defining the operational states of your pattern detector 2) Draw a schematic diagram of the "101" pattern detector circuit using a 7473 IC. 3) Build the circuit on a breadboard.
4) Test the circuit and verify its operation matches the requirements.
5) Demonstrate your circuit operation to your instructor to verify its operation.
As this is the final lab for this course, it is expected that your lab report will be written in a most professional manner, and will include the following items:
a. A detailed description of the use, purpose and operation of the "State Diagram".
b. Accurate labeling and descriptions of the logic tables and diagrams needed
to create your solution.
c. A detailed schematic of the circuit built for the solution.
d. A detailed timing diagram representing the solution.
At this point in your Digital Logic career, an assignment comes where you need to put all your knowledge of J-K flip-flops
Please send an easy to read circuit design as well and explain how it works. 4:02 00 LTE il 50% + ENEE 2586 - Lab 9_f... @ + : ENEF 356 Lab -Sequence Detector ENEE 2586 Lab #9 - Sequence Detector Purpose: The goal of this lab is to design a sequence detector using sequential logic circuits Procedure: 1. Design a sequential logic circuit to check an input stream labeled X and to produce an output Z=1 for any input...
The lab can be made in orcad but all I need is how to and the design. Please Read the problem carefully and answer as much as you can. Thank you!!! Part 2 T and D from JK 1. Using part 74107 (JK flip-flop), build a T and a D-flip. Do NOT put both designs on the same schematic page or in the same folder. 2. Create parts for each and run a simulation using the parts created. Part 3....
Its logic design my sequence is 127605 i need help with all this pages please and thank you 27 60 Experiment 4 Six-State Up-Down Counter 1 Objective To become familiar with the design procedures of a counter, which are applicable to the design of other synchronous sequential circuits. 2 Problem description A six-state up-down counter is to be designed. Three flip-flops with outputs Q2,Qi and Qo are required in the design. As shown in Figure 1, the counter is initialized...
Digital Logic Design Need help with homework. Also need to create Logisim circuit with results. Thank you! Your IDs gn project, spring semester Your name 19 Digital Logic Design. Mid-semester desi This is a synchronous counter design. Tables and Karnaugh maps are provided. Do this alone, do not consult with friends except for general structions guidance-I want to see your design. Design, Synchronous counter. (#2 of 3) (repeat). That is QdQcQbQa-0001 (one), 0010 (t Note: Qa is the I.s.b. Design...
Using J-K, D, T and D flip- flops in the following order as seen in the table; fill out the next state table that only follows the cycles of the state diagram cycle seen above. After this is done draw the proper logic circuit to run it in a simulator to see that it is working properly and the tables where filled in the proper way. IT IS SUPPOSE TO STOP ONCE IT REACHES 0000. IT ONLY RUNS THE CYCLE...
Using J-K, D, T and D flip- flops in the following order as seen in the table; fill out the next state table that only follows the cycles of the state diagram cycle seen above. After this is done draw the proper logic circuit to run it in a simulator to see that it is working properly and the tables where filled in the proper way. IT IS SUPPOSE TO STOP ONCE IT REACHES 0000. IT ONLY RUNS THE CYCLE...