Question

Problems 1075 Transistor Q3 WIL (um/um) 36/0.3 36/0.3 6/0.3 6/0.3 30/0.3 W/0.3 45/0.3 6/0.3 and A, if all devices are 0.3 m long, Q and Q2 are operated at overdrive voltages of 0.15-V magnitude, and Q is operated at Voy 0.2 V. Also, determine the op-amp output resistance 100 k2, C0.1 pF, G = 2 mA/V, R, = 50 k2, and C 2 pF. (a) Find the dc gain. (b) Without C connected, find the frequencies of the two poles in radians per second and sketch a Bode plot for the gain magnitude. (c) With Ce connected, find p. Then find the value of C that will result in a unity-gain frequency , at least two octaves below a. For this value of C¢, find p and a and sketch a Bode plot for the gain magnitude. obtained when the second stage is biased at 0.3 mA. What do you expect the output resistance of a unity-gain voltage amplifier to be, using this op amp? D 13.3 The CMOS op amp of Fig. 13.1 is fabricated in for all devices is 20 V/um a process for which V If all transistors have L0.3 um and are operated at equal overdrive voltages, find the magnitude of the over- drive voltage required to obtain a of 1600 V/V dc open-loop gain 13.8 A CMOS op amp with the topology in Fig. 13.1 has mA/V, g 3 mA/V, the total capacitance between node D2 and ground is 0.2 pF, and the total 13.4 Consider the circuit in Fig. 13. with the device geo- metries shown at the top of this page. Let I40 PA, capacitance between the output node and ground is 3 pF. Find v for all devices=0.45 V, 4_C=270 pA/V, u,C 70LA/V for all devices = 15 V, Vp = Vs= 1 V. Determine the width of Q W, that will ensure that the op amp will not have a systematic offset voltage. Then, for al devices, evaluate IVov|,Vs Provide your results in a table. Also find A, A, the dc opcn-loop voltage gain, the input common-mode range, and the output voltage range. Neglect the effect of V on the bias currents the value of Cc that results inf, 50 MHz, and verify that f is lower than fz and f = 13.9 A particular design of the two-stage CMOS op amp of Fig. 13.1 has G = 1 mA/V and C 2 mA/V. The gand total capacitance at the output node is 1 pF. While utilizing Miller compensation capacitor C without a series resistance R, the amplifier is made to have a uniform -20-dB/decade gain rolloff with a unity-gain frequency f of 100 MHz. (a) What must the value of C be? (b) What do you estimate the frequencies of the poles, fp and f and of the right-half-plane zero, fz, to be? D 13.5 Design the two-stage CMOS op amp in Fig. 13.1 to provide a CMRR of about 72 dB. If all the transistors are operated at equal overdrive voltages of 0.15 V and have equal channel lengths, find the minimum required channel length For this technology, |vá| = 15 V/um. What is the de gain (c) What is the phase margin obtained? (d) To increase the phase margin, a resistance R is connected in series with Ce. What is the value of R that results in f00, and what is the resulting phase margin? realized? 13.6 A two-stage CMOS op amp has G 0.8 mA/V, G 2.4mA/V, C,=0.1 pF, and C=1.2 pF. Find the value of Ce that will provide a unity-gain frequency of 120 MHz Also, determine the values of f and f. (e) If R is increased further, until it moves the zero into the left half-plane and thus turns the phase it introduces into phase lead, what value of R is needed to obtain a phase margin of 85? 13.7 For the CMOS amplifier in Fig. 13.1, whose equivalent D13.10 A particular implementation of the CMOS ampli- circuit is shown in Fig. 13.2, let G = 1 mA/V, R = fier of Figs. 13.1 and 13.2 provides G = 0.3 mA/V, Multisim/PSpice; difficult problem; SIM very challenging: D design problem more difficult CHAPTER 13 PROBLEMS

sedra smith book 7th edition chapter name is operational amplifier. question 12.1 to 12.10 I need all solution with good hand writing.

Answer 1

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