Question

CLK CLK CLK CLK Gate 5 Gate 6 CLK CLK Q D CLK CLK Cioad Cload load Cload Gate 2 Gate 3 Gate 1 Gate 3 Consider above sequential circuit. Problem 4.1 (4 points) Is this circuit a static or dynamic sequential element (circle one)? Justify your answer Static Dynamic Problem 4.2 (6 points) Is this a level sensitive latch or an edge sensitive register? If it is a latch, which clock phase makes the latch transparent, low or high? If it is a register, which edge is the data sampling edge: rising edge or falling edge? Latch? If so, which clock phase makes the latch transparent, low or Register? If so, which edge is the data sampling edge: rising edge or falling edge? Problem 4.3 (8 points) Please identify the delay time of tsetun and t You do not need to high? calculate the delay number. But you have to identify which gate delay should be include. Use the gate name indicated on the figure above.

Answer 1

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