Question

2. (15 points total, 3 pts each) Let’s say that we have a 4-way set associative...

2. (15 points total, 3 pts each) Let’s say that we have a 4-way set associative cache. The cache has 16 sets in total. Main memory consists of 16K blocks of 16 words each, and word addressing is used. a. Show the address format that is used to map main memory address to the cache. Include the appropriate fields and their sizes. For the remaining questions, assume that we have the following situation: We have a program that loops 6 times from location 1209810 in memory to location 1238610. In other words, think of this as an assembly language program that runs from the opcode at location 12098 to the opcode at location 12386, then loops back to location 12098. It does 6 such iterations in total (the original pass, plus 5 more loops). You can assume that the cache is initially empty. b. At the end of the first iteration, how many blocks of memory are stored in the cache? c. At the end of the first iteration, how many of these blocks are stored in (i) Set 2 (ii) Set 5 d. At the end of the first iteration, what is the hit ratio for the cache? The hit ratio should be expressed as a percentage (e.g., 85.67% or 96.35%) e. At the end of all 6 iterations, what is the hit ratio for the cache?

0 0
Add a comment Improve this question Transcribed image text
Answer #1

Given

  • 4-way set associative cache
  • cache has 16 sets
  • Main memory consists of 16K blocks
  • 16 words per block

a) Show the address format that is used to map main memory address to the cache.

Main memory consists of 16K blocks each block with 16 words => 2^18 words

=>  address has 18 bits

cache has 16 sets in total and it is 4-way set associative cache

Number of bits to represent set = 2^4/2^2

= 2^2

=> 2 bits

16 words per block  

Number of bits to represent block = 2^4

=> 4 bits

Number of bits to represent tag = 18 - 2 - 4

= 12 bits

address format => (0-3) bits represent word in block

(4-5) bits represent set in cache

(6-17) bits represent tag   

Now, there is a program that runs from the opcode at location 12098 to the opcode at location 12386, then loops back to location 12098 six times.

cache is initially empty and on a request, the entire block is brought into the cache

12098 - (000010111101000000)2 placed @set 0, line 0 => words from 12099 to 12113 are also brought inside ( referring these will always be a cache hit => for one block there is 13 cache hits)

12114 - (000010111101010010)2   placed @set 1, line 0 => words from 12115 to 12129 are also brought inside

12130 - (000010111101100010)2   placed @set 0, line 1 => words from 12131 to 12145 are also brought inside

12146 - (000010111101110010)2   placed @set 3, line 0 => words from 12146 to 12161 are also brought inside

12162 - (000010111110000010)2   placed @set 0, line 2 => words from 121463 to 12177 are also brought inside

12178 - (000010111110010010)2   placed @set 1, line 1 => words from 121479 to 12193 are also brought inside

12194 - (000010111110100010)2   placed @set 1, line 2 => words from 12195 to 12209 are also brought inside

12210 - (000010111110110010)2   placed @set 3, line 1 => words from 12211 to 12225 are also brought inside

12226 - (000010111111000010)2   placed @set 0, line 3 => words from 12227 to 12241 are also brought inside

12242 - (000010111111010010)2   placed @set 1, line 3 => words from 12243 to 12257 are also brought inside

12258 - (000010111111100010)2   placed @set 2, line 0 => words from 12259 to 12273 are also brought inside

12274 - (000010111111110010)2   placed @set 3, line 2 => words from 12275 to 12289 are also brought inside

12290 - (000011000000000010)2   placed @set 0, line 0 => words from 12291 to 12305 are also brought inside

12306 - (000011000000010010)2   placed @set 1, line 0 => words from 12307 to 12321 are also brought inside

12322 - (000011000000100010)2   placed @set 2, line 1 => words from 12323 to 12337 are also brought inside

12338 - (000011000000110010)2   placed @set 3, line 3 => words from 12339 to 12353 are also brought inside

12354 - (000011000001000010)2   placed @set 0, line 1 => words from 12355 to 12369 are also brought inside

12370 - (000011000001010010)2   placed @set 2, line 2 => words from 12371 to 12385 are also brought inside

12386 - (000011000001100010)2   placed @set 2, line 3 => words from 12387 to 12401 are also brought inside

b) At the end of the first iteration, how many blocks of memory are stored in the cache?

Set 0 - holds 4 blocks

Set 1 - holds 4 blocks

Set 2 - holds 4 blocks

Set 3 - holds 4 blocks

all sets are full => cache contains 16 blocks of memory

c) At the end of the first iteration, how many of these blocks are stored in

(i) Set 2 - 4 blocks

(ii) Set 5 - 4 blocks

d) At the end of the first iteration, what is the hit ratio for the cache?

18 + 1 complusory misses

Whenever there is a miss, a block is placed inside cache => 15 other words can be referenced directly

=> 15 hits/block

Number of reference = 18*16 + 1 = 289

Number of hits = 18*15 = 270

Hit ratio = 270/289 = 0.9342

= 93.42%

Add a comment
Know the answer?
Add Answer to:
2. (15 points total, 3 pts each) Let’s say that we have a 4-way set associative...
Your Answer:

Post as a guest

Your Name:

What's your source?

Earn Coins

Coins can be redeemed for fabulous gifts.

Not the answer you're looking for? Ask your own homework help question. Our experts will answer your question WITHIN MINUTES for Free.
Similar Homework Help Questions
  • Let’s say that we have a 4-way set associative cache. The cache has 16 sets in...

    Let’s say that we have a 4-way set associative cache. The cache has 16 sets in total. Main memory consists of 16K blocks of 16 words each, and word addressing is used. a. Show the address format that is used to map main memory address to the cache. Include the appropriate fields and their sizes. For the remaining questions, assume that we have the following situation: We have a program that loops 6 times from location 1209810 in memory to...

  • 6. A 2-way set associative cache consists of four sets. Main memory contains 2K blocks of...

    6. A 2-way set associative cache consists of four sets. Main memory contains 2K blocks of eight words each. a. Show the main memory address format that allows us to map addresses from main memory to cache. Be sure to include the fields as well as their sizes. b. Compute the hit ratio for a program that loops 5 times from locations 8 to 51 in main memory. You may leave the hit ratio in terms of a fraction.

  • A 2-way set associative cache consists of four sets 0, 1, 2, 3. The main memory...

    A 2-way set associative cache consists of four sets 0, 1, 2, 3. The main memory is word addressable (i.e. treat the memory as an array of words indexed by the address). It contains 2048 blocks 0 through 2047, and each block has eight words. (a) How many bits are needed to address the main memory? (b) Show how a main memory address will be translated into a tag, a set number, and an offset within a block. Illustrate this...

  • 1. 2-way Set Associative Cache Memory Consider a hypothetical machine with 1K words of cache memo...

    1. 2-way Set Associative Cache Memory Consider a hypothetical machine with 1K words of cache memory. They are in two-way set associative organization, with cache block size of 128 words, using LRU replacement algorithm. Suppose the cache hit time is 9ns, the time to transfer the first word from main memory to cache is 50ns, while subsequent words require 10ns/word. Consider the following read pattern (in blocks of 128 words, and block id starts from 0): 1 2 3 5...

  • Consider a 2-way set associative cache consisting of 8 blocks total of byte-addressable memory with 4...

    Consider a 2-way set associative cache consisting of 8 blocks total of byte-addressable memory with 4 bytes per block. Assume that the cache is initially empty. Given the following address sequence, fill in the table below. Time Access Tag Set Offset 3 10010001 11001001 10110110 10101011 10110010

  • You have a 2-way set associative L1 cache that is 8KB, with 4-word cache lines. You get the follo...

    You have a 2-way set associative L1 cache that is 8KB, with 4-word cache lines. You get the following sequence of writes to the cache --each is a 32-bit address in hexadecimal 0x32E4 0x8000 0x1F50 0x8004 0x72EC OxDOOC 0x800C 0x72E8 0x4008 OxD000 0x82E0 a) [7 Pts] How many cache misses occur with an LFU (Least Frequently Used) policy? Give a detailed answer and fill in the table below for each address reference Set Index (in hex) Memory address(in hex) 0x32E4...

  • 6. What is the difference between a Direct map cache and Set associative cache. If we...

    6. What is the difference between a Direct map cache and Set associative cache. If we are looking for block #26, block 32 and block #10 in an 8 way set associative and 4 block direct mapped cache. Where can we find these blocks. (Show your work) 7. What are the differences between SRAM, DRAM, SDRAM, who implements SRAM and SDRAM 8. What is a DIMM, So-Dimm and DDR, list different versions of DDR, what are the differences between those...

  • 18. You have a byte-addressable virtual memory system with a two-entry TLB, a 2-way set associati...

    18. You have a byte-addressable virtual memory system with a two-entry TLB, a 2-way set associative cache, and a page table for a process P. Assume cache blocks of 8 bytes and page size of 16 bytes. In the system below, main memory is divided into blocks, where each block is represented by a letter. Two blocks equal one frame. Given the system state as depicted above, answer the following questions: a) How many bits are in a virtual address...

  • 3. 12+2-4 points] We are comparing the two caches in Problem 1 and Problem 2. Suppose both caphes have a hit time of 2 cycles. The cache in Problem 1 has a miss penalty of 15 cycles. The o...

    3. 12+2-4 points] We are comparing the two caches in Problem 1 and Problem 2. Suppose both caphes have a hit time of 2 cycles. The cache in Problem 1 has a miss penalty of 15 cycles. The one in Problem 2 has a miss penalty of 25 cycles. Calculate the total time taken (in cycles) for all accesses, for each cache. Which cache is better- the one in Problem 1 or Problem 2? 3. 12+2-4 points] We are comparing...

  • Suppose we have a 32-bit MIPS processor, which includes a 2-way set associative data cache with...

    Suppose we have a 32-bit MIPS processor, which includes a 2-way set associative data cache with capacity 16384 bytes, 16 bytes block, and a least recently used (LRU) replacement policy. Assume that the cache is empty (all valid bits are 0) before the following code is executed. lw $t1, 0x1040($0) lw $t2, 0x2044($0) lw $t3, 0x3048($0) lw $t4, 0x1044($0) lw $t5, 0x504c($0) lw $t6, 0x3040($0) For each of the six assembly instructions above, state i) the set field value for...

ADVERTISEMENT
Free Homework Help App
Download From Google Play
Scan Your Homework
to Get Instant Free Answers
Need Online Homework Help?
Ask a Question
Get Answers For Free
Most questions answered within 3 hours.
ADVERTISEMENT
ADVERTISEMENT
ADVERTISEMENT