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*Design an arithmetic circuit with two selection variables S1 and S0 and t won-bit data inputs A and B. The circuit generates the following eight arithmetic operations in conjunction with carry Cin:
S1 | S2 | Cin=0 | Cin=1 |
0 | 0 | F=A+B(add) | F=A+ +1(Subtract A-B) |
0 | 1 | F=+B | F=+B+1(Subtract B–A) |
1 | 0 | F=A–1 (decrement) | F=A+1 (increment) |
1 | 1 | F=(1s complement) | F=+1(2s complement) |
Draw the logic diagram for the two least significant bits of the arithmetic circuit.
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