The single-cycle computer in Figure 1 executes the five instructions described by the regi...

The single-cycle computer in Figure 1 executes the five instructions described by the register transfers in the table that follows.

(a) Complete the following table, giving the binary instruction decoderoutputs from Figure 2 during execution of each of the instructions:

Instruction–Register Transfer	DA	AA	BA	BA	FS	MD	RW	MW	PL	JB
R[0]←R[7]⨁R[3]
R[1]←M[R[4]]
R[2]←R[5]+2
R[3]←s1R[6]
If (R([4]=0) PC←PC+se AD else PC← PC +1

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(b) Complete the following table, giving the instruction in binary for the single-cycle computer that executes the register transfer (if any field is not used, give it the value 0):

Instruction–Register Transfer	Opcode	DR	SA	SB or Operand
R[0]←R[7]+R[6]
R[1]←R[5]–1
R[2]←s1R[4]
R[4]←R[2]VR[1]

Figure 1 Block Diagram for a Single-Cycle Computer

Figure 2 Diagram of Instruction Decoder