The plus (+) indicates a more advanced problem and the asterisk (*) indicates that a solut...

The plus (+) indicates a more advanced problem and the asterisk (*) indicates that a solution is available on the Companion Website for the text.

+A new instruction, SMR (Store Multiple Registers), with symbolic opcode name SMR, is to be implemented for the multiple-cycle computer. The instruction stores the contents of eight registers in eight consecutive memory locations. Register R[SA] specifies the address in memory M to which the first register R[SB] is to be stored. The registers to be stored ar modulo 8], . . ., R[(SB+7) modulo 8] in Memory M addresses. Design this instruction presenting your final results in the form shown in Table. [Hint: In order to address all eight registers, it is necessary to provide eight values of SB in the Instruction Register. Since the Instruction Register can only be loaded from memory, these “instructions” must be placed in memory temporarily during the instruction execution and loaded into the IR as data without using the usual instruction fetch.]

Table State Table for Illustration of Instructions Having Three or More Cycles