Figure shows two series transistors modeling the pulldown network of 2-input NAND gate.a)...

Figure shows two series transistors modeling the pulldown network of 2-input NAND gate.

a) Plot I vs. A using long-channel transistor models for 0 ≤ A ≤ 1, B = Y = 1, Vt = 0, β = 1. On the same axes, plot I vs. B for 0 ≤ B ≤ 1, A = 1. Hint: You will need to solve for x; this can be done numerically.

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b) Using your results from (a), explain why the inner input of a 2-input NAND gate has a slightly greater logical effort than the outer input.

FIGURE Current in series transistors