Simulate each gate you designed in Exercise Determine the average delay (or rising delay for the domino design). Logical effort is only an approximation. Tweak the transistor sizes to improve the delay. How much improvement can you obtain?
Exercise
Design a fast 6-input OR gate in each of the following circuit families. Sketch an implementation using two stages of logic (e.g., NOR6 + INV, NOR3 + NAND2, etc.). Label each gate with the width of the pMOS and nMOS transistors. Each input can drive no more than 30 λ of transistor width. The output must drive a 60/30 inverter (i.e., an inverter with a 60 λ wide pMOS and 30 λ wide nMOS transistor). Use logical effort to choose the topology and size for least average delay. Estimate this delay using logical effort. When estimating parasitic delays, count only the diffusion capacitance on the output node.
a) static CMOS
b) pseudo-nMOS with pMOS transistors 1/4 the strength of the pulldown stack
c) domino (a footed dynamic gate followed by a HI-skew inverter); only optimize the delay from rising input to rising output
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