An incomplete ASMD chart for a finite state machine is shown in Fig. P8.29 . The registe...

An incomplete ASMD chart for a finite state machine is shown in Fig. P8.29 . The register operations are not specified, because we are interested only in designing the control logic.

(a) Draw the equivalent state diagram.

(b) Design the control unit with one flip-flop per state.

(c) List the state table for the control unit.

(d) Design the control unit with three D flip-flops, a decoder, and gates.

(e) Derive a table showing the multiplexer input conditions for the control unit.

(f) Design the control unit with three multiplexers, a register with three flip-flops, and a 3 ×8 decoder.

(g) Using the results of (f), write and verify a structural model of the controller.

(h) Write and verify an RTL description of the controller.