The block diagram and partially completed ASMD chart in Fig. P8.41 describe the behavior...

The block diagram and partially completed ASMD chart in Fig. P8.41 describe the behavior of a two-stage pipeline that acts as a 2:1 decimator with a parallel input and output. Decimators are used in digital signal processors to move data from a datapath with a high clock rate to a datapath with a lower clock rate, converting data from a parallel format to a serial format in the process. In the datapath shown, entire words of data can be transferred into the pipeline at twice the rate at which the contents of the pipeline must be dumped into a holding register or consumed by some processor. The contents of the holding register R0 can be shifted out serially, to accomplish an overall parallel-to-serial conversion of the data stream. The ASMD chart indicates that the machine has synchronous reset to S_idle, where it waits until rst is de-asserted and En is asserted. Note that synchronous transitions which would occur from the other states to S_idle under the action of rst are not shown. With En asserted, the machine transitions from S_idle to S_1, accompanied by concurrent register operations that load the MSByte of the pipe with Data and move the content of P1 to the LSByte ( P0 ). At the next clock, the state goes to S_full, and now the pipe is full. If Ld is asserted at the next clock, the machine moves to S_1 while dumping the pipe into a holding register R0 . If Ld is not asserted, the machine enters S_wait and remains there until Ld is asserted, at which time it dumps the pipe and returns to S_1 or to S_idle, depending on whether En is asserted, too. The data rate at R0 is one-half the rate at which data are supplied to the unit from an external datapath.

(a) Develop the complete ASMD chart.

(b) Using the ASMD chart developed in (a), write and verify an HDL model of the datapath.

(c) Write and verify a Verilog behavioral model of the control unit.

(d) Encapsulate the datapath and controller in a top-level module, and verify the integrated system.