Modify the block diagram of the sequential multiplier given in Fig. 8.14 (a) and the ASM...

Modify the block diagram of the sequential multiplier given in Fig. 8.14 (a) and the ASMD chart in Fig. 8.15 (b) to describe a system that multiplies 32-bit words, but with 8-bit (bytewide) external datapaths. The machine is to assert Ready in the (initial) reset state. When Start is asserted, the machine is to fetch the data bytes from a single 8-bit data bus in consecutive clock cycles (multiplicand bytes first, followed by multiplier bytes, least significant byte first) and store the data in datapath registers. Got_Data is to be asserted for one cycle of the clock when the transfer is complete. When Run is asserted, the product is to be formed sequentially. Done_Product is to be asserted for one clock cycle when the multiplication is complete. When a signal Send_Data is asserted, each byte of the product is to be placed on an 8-bit output bus for one clock cycle, in sequence, beginning with the least significant byte. The machine is to return to the initial state after the product has been transmitted. Consider safeguards, such as not attempting to send or receive data while the product is being formed. Consider also other features that might eliminate needless multiplication by 0. For example, do not continue to multiply if the shifted multiplier is empty of 1’s.