After doing Exercise 1, write a VHDL test bench that tests the adder for all possible pair...

After doing Exercise 1, write a VHDL test bench that tests the adder for all possible pairs of 4-bit addends, and displays any incorrect results.

Exercise 1

Instantiating multiple copies of the module that you designed in Exercise 2, write a structural VHDL program for a 4-bit ripple adder using the structure of Figure 6-84.

Exercise 2

Write a dataflow-style VHDL program (entity and architecture) corresponding to the full-adder circuit in Figure 6-83.