After doing Exercise 1, write a VHDL test bench that tests the adder for a subset of the 2...

After doing Exercise 1, write a VHDL test bench that tests the adder for a subset of the 232 possible pairs of 16-bit addends, and displays any incorrect results. Try to come up with a strategy for generating the input pairs that catches likely coding errors while using less than a million input combinations.

Exercise 1

Using the entity that you defined in Exercise 2, write a structural VHDL program for a 16-bit ripple adder along the lines of Figure 6-84. Use a generate statement to create the 16 full adders and their signal connections.

Exercise 2

Write a dataflow-style VHDL program (entity and architecture) corresponding to the full-adder circuit in Figure 6-83.