After completing the preceding exercise, write a Verilog test bench that compares the outp...

After completing the preceding exercise, write a Verilog test bench that compares the outputs of your circuit for all possible input combinations against results computed by the simulator using its own arithmetic. The test bench should stop and display the actual and computed outputs if there is a mismatch. Test your test bench by putting a bug in your original Verilog program and running the test bench. Extra credit (in your own mind only) if you already had an unknown bug in the original program!